An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Verification Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers
On the Design of Multiple Fault Diagnosable Networks
IEEE Transactions on Computers
Algorithms for Detection of Faults in Logic Circuits
IEEE Transactions on Computers
Fault Equivalence in Combinational Logic Networks
IEEE Transactions on Computers
Multiple Fault Testing of Large Circuits by Single Fault Test Sets
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
A New Representation for Faults in Combinational Digital Circuits
IEEE Transactions on Computers
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Multiple fault detection using single stuck-at fault test sets is considered. The 74LS181 4-bit ALU is analyzed using 10 test sets varying widely in length and method of generation. The simulation results demonstrate significantly higher multiple fault coverage than anticipated by previous studies. It is shown that single stuck-at fault test sets can provide suitably high fault coverage for practical circuits with multiple outputs and reconvergent internal fanout.