Comments on "Detection of Faults in Programmable Logic Arrays"
IEEE Transactions on Computers
The Boolean Difference and Multiple Fault Analysis
IEEE Transactions on Computers
Multiple Fault Detection in Combinational Circuits: Algorithms and Computational Results
IEEE Transactions on Computers
Generic Fault Characterizations for Table Look-Up Coverage Bounding
IEEE Transactions on Computers
Minimal Redundant Logic for High Reliability and Irredundant Testability
IEEE Transactions on Computers
Multiple Fault Testing of Large Circuits by Single Fault Test Sets
IEEE Transactions on Computers
IEEE Transactions on Computers
An analysis of the multiple fault detection capabilities of single stuck-at fault test sets
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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This paper considers the design of diagnosable combinational networks. The diagnosability criterion used here requires that the single fault detection test set for the network also detects all multiple faults. Several recent studies in the area of multiple fault diagnosis are reviewed and the results which are pertinent to this investigation are summarized. It is shown that, under certain conditions, internal fan-out may be present without adversely affecting the detection of multiple faults. These results suggest design techniques which lead to readily diagnosable networks.