Multiple Fault Detection in Combinational Networks
IEEE Transactions on Computers
Analyzing Errors with the Boolean Difference
IEEE Transactions on Computers
On the Design of Multiple Fault Diagnosable Networks
IEEE Transactions on Computers
An Efficient Algorithm for Generating Complete Test Sets for Combinational Logic Circuits
IEEE Transactions on Computers
Path Sensitization, Partial Boolean Difference, and Automated Fault Diagnosis
IEEE Transactions on Computers
Design for Testability A Survey
IEEE Transactions on Computers
Generic Fault Characterizations for Table Look-Up Coverage Bounding
IEEE Transactions on Computers
Multiple Fault Detection in Programmable Logic Arrays
IEEE Transactions on Computers
Resolution-Oriented Fault Interrelationships in Combinational Logic Networks
IEEE Transactions on Computers
On the Existence of Combinational Logic Circuits Exhibiting Multiple Redundancy
IEEE Transactions on Computers
LSI logic testing: an overview
IEEE Transactions on Computers
A Probabilistic Approach to Diagnose SETs in Sequential Circuits
Journal of Electronic Testing: Theory and Applications
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The Boolean difference is a well-known mathematical concept which has found significant application in the single fault analysis of combinational logic circuits. One of the primary attributes of the Boolean difference in such situations is its completeness. In this paper we extend the Boolean difference concept to cover multiple fault situations. Expressions are developed which give all possible input patterns that can be applied to combinational logic circuits to demonstrate the presence or absence of a specified multiple fault of the stuck-type class. Such expressions are useful in situations where at most, say, p simultaneous faults need be considered, as well as situations where any multiple fault can exist. In addition the expressions developed are also shown to complete some existing single fault analysis concepts.