The Boolean Difference and Multiple Fault Analysis
IEEE Transactions on Computers
Comments on "Multiple Fault Detection in Combinational Networks"
IEEE Transactions on Computers
The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's
IEEE Transactions on Computers
Generic Fault Characterizations for Table Look-Up Coverage Bounding
IEEE Transactions on Computers
Fault Masking in Combinational Logic Circuits
IEEE Transactions on Computers
A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays
IEEE Transactions on Computers
Multiple Fault Detection in Programmable Logic Arrays
IEEE Transactions on Computers
Properties of Faults and Criticalities of Values under Tests for Combinational Networks
IEEE Transactions on Computers
Minimal Redundant Logic for High Reliability and Irredundant Testability
IEEE Transactions on Computers
Fault Detection in Fanout-Free Combinational Networks
IEEE Transactions on Computers
Multiple Fault Testing of Large Circuits by Single Fault Test Sets
IEEE Transactions on Computers
Resolution-Oriented Fault Interrelationships in Combinational Logic Networks
IEEE Transactions on Computers
Algebraic Properties of Functions Affecting Optimum Fault-Tolerant Realizations
IEEE Transactions on Computers
On the Existence of Combinational Logic Circuits Exhibiting Multiple Redundancy
IEEE Transactions on Computers
Identification of Multiple Stuck-Type Faults in Combinational Networks
IEEE Transactions on Computers
An improved soft-error rate measurement technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
| Hi-index | 15.03 |
Combinational networks with no internal fan-out are considered from the point of view of testing for multiple faults. Several different approaches utilizing added inputs and observable outputs are considered and the tradeoffs are discussed.