Multi-level logic simplification using don't cares and filters
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The use of observability and external don't cares for the simplification of multi-level networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
On removing multiple redundancies in combinational circuits
Proceedings of the conference on Design, automation and test in Europe
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Constructive Analysis of Cyclic Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A robust algorithm for approximate compatible observability don't care (CODC) computation
Proceedings of the 41st annual Design Automation Conference
SAT-Based Complete Don't-Care Computation for Network Optimization
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
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HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
SAT sweeping with local observability don't-cares
Proceedings of the 43rd annual Design Automation Conference
Stepping forward with interpolants in unbounded model checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Boosting interpolation with dynamic localized abstraction and redundancy removal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multiple Fault Detection in Combinational Networks
IEEE Transactions on Computers
Logic Transformations by Multiple Wire Network Addition
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
Automated abstraction by incremental refinement in interpolant-based model checking
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Optimal constraint-preserving netlist simplification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Trading-off SAT search and variable quantifications for effective unbounded model checking
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Exploiting constraints in transformation-based verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
LOT: Logic Optimization with Testability. New transformations for logic synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper introduces an approach to effectively exploit incremental SAT in order to search for multiple equivalence-preserving transformations of combinational circuits. Typical applications, such as redundancy removal with observability and external care conditions, adequate abstractions and other optimizations used in a state-of-the-art SAT-based model checker, can reap benefits from the proposed strategies. Our techniques exploit SAT incrementality, by iteratively refining the set of candidate transformations with a counter-example driven analysis, until an unsatisfiable point is reached. The key point of our technique is the ability to address satisfiable instances first, where SAT solvers are generally much faster than with unsatisfiable runs. We also discuss partitioning and problem reduction issues, that are fundamental in order to provide a scalable approach. Experimental results show the effectiveness of the proposed strategies.