Multi-level logic simplification using don't cares and filters

Authors:
A. Saldanha;A. R. Wang;R. K. Brayton;A. L. Sangiovanni-Vincentelli
Affiliations:
EECS Department, University of California, Berkeley, Berkeley, CA;EECS Department, University of California, Berkeley, Berkeley, CA;EECS Department, University of California, Berkeley, Berkeley, CA;EECS Department, University of California, Berkeley, Berkeley, CA
Venue:
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Year:
1989

Citing 1
Cited 13

Logic Minimization Algorithms for VLSI Synthesis

Logic Minimization Algorithms for VLSI Synthesis

Boolean resubstitution with permissible functions and binary decision diagrams

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The use of observability and external don't cares for the simplification of multi-level networks

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Optimization of primitive gate networks using multiple output two-level minimization

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Optimum functional decomposition using encoding

DAC '94 Proceedings of the 31st annual Design Automation Conference
Efficient use of large don't cares in high-level and logic synthesis

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
BooleDozer: logic synthesis for ASICs

IBM Journal of Research and Development
Maximum projections of don't care conditions in a Boolean network

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis

EURO-DAC '91 Proceedings of the conference on European design automation
SAT sweeping with local observability don't-cares

Proceedings of the 43rd annual Design Automation Conference
Sequential Circuits for Relational Analysis

ICSE '07 Proceedings of the 29th international conference on Software Engineering
Sequential circuits for program analysis

Proceedings of the twenty-second IEEE/ACM international conference on Automated software engineering
Mapping for better than worst-case delays in LUT-based FPGA designs

Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Finding Multiple Equivalence-Preserving Transformations in Combinational Circuits through Incremental-SAT

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

Simplication of a multi-level network is used to perform transformations on parts of the network to obtain an alternate structure that is optimal with respect to area. A technique for obtaining such an optimal structure involves the use of two-level logic minimization on the components of the multi-level logic network. At each component, the structure of the network is captured by intermediate and fan-out don't care sets, which are utilized in the two-level minimization. However, the generation of all the don't cares yield very large sets for most networks and consequently the complete minimization of the components of the circuits require a very large amount of computer time.In this paper we describe algorithms to reduce the size of the don't care sets, so that only the portions that will be useful in minimization at each component of the circuit are retained. We develop both an exact filter and a heuristic filter that prove to be very effective for a large set of benchmark examples. Results show that our technique achieves the same quality as that obtained by doing complete minimizations at each component of the circuits but in much shorter time. This new approach to simplification of multi-level networks has been incorporated into the MIS (version 2.1) logic synthesis system.