Multi-level logic simplification using don't cares and filters
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The use of observability and external don't cares for the simplification of multi-level networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Using SAT for combinational equivalence checking
Proceedings of the conference on Design, automation and test in Europe
Compatible observability don't cares revisited
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Managing Don't Cares in Boolean Satisfiability
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A robust algorithm for approximate compatible observability don't care (CODC) computation
Proceedings of the 41st annual Design Automation Conference
A Circuit SAT Solver With Signal Correlation Guided Learning
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
SAT-Based Complete Don't-Care Computation for Network Optimization
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Considering Circuit Observability Don't Cares in CNF Satisfiability
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the 2005 international symposium on Physical design
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Logic optimization and equivalence checking by implication analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Boolean reasoning for equivalence checking and functional property verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Alembic: an efficient algorithm for CNF preprocessing
Proceedings of the 44th annual Design Automation Conference
Enhancing design robustness with reliability-aware resynthesis and logic simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Optimizing non-monotonic interconnect using functional simulation and logic restructuring
Proceedings of the 2008 international symposium on Physical design
Merging nodes under sequential observability
Proceedings of the 45th annual Design Automation Conference
Scalable don't-care-based logic optimization and resynthesis
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Optimal constraint-preserving netlist simplification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Automatic formal verification of block cipher implementations
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Property based coverage criterion
Proceedings of the 2nd International Workshop on Defects in Large Software Systems: Held in conjunction with the ACM SIGSOFT International Symposium on Software Testing and Analysis (ISSTA 2009)
Simulation and SAT-based Boolean matching for large Boolean networks
Proceedings of the 46th Annual Design Automation Conference
Proceedings of the 46th Annual Design Automation Conference
Signature-based SER analysis and design of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast detection of node mergers using logic implications
Proceedings of the 2009 International Conference on Computer-Aided Design
DeltaSyn: an efficient logic difference optimizer for ECO synthesis
Proceedings of the 2009 International Conference on Computer-Aided Design
Journal of Electronic Testing: Theory and Applications
Partitioning interpolant-based verification for effective unbounded model checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Node addition and removal in the presence of don't cares
Proceedings of the 47th Design Automation Conference
LUT-based FPGA technology mapping for reliability
Proceedings of the 47th Design Automation Conference
Making deduction more effective in SAT solvers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Leveraging dominators for preprocessing QBF
Proceedings of the Conference on Design, Automation and Test in Europe
Optimizing blocks in an SoC using symbolic code-statement reachability analysis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Fast node merging with don't cares using logic implications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Coping with Moore's law (and more): supporting arrays in state-of-the-art model checkers
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Interpolation-based incremental ECO synthesis for multi-error logic rectification
Proceedings of the 48th Design Automation Conference
Scalable don't-care-based logic optimization and resynthesis
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Match and replace: a functional ECO engine for multi-error circuit rectification
Proceedings of the International Conference on Computer-Aided Design
Generalized SAT-sweeping for post-mapping optimization
Proceedings of the 49th Annual Design Automation Conference
ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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SAT sweeping is a method for simplifying an shape And/Inverter graph (AIG) by systematically merging graph vertices from the inputs towards the outputs using a combination of structural hashing, simulation, and SAT queries. Due to its robustness and efficiency, SAT sweeping provides a solid algorithm for Booleanreasoning in functional verification and logic synthesis. In previous work, SAT sweeping merges two vertices only if they are functionally equivalent. In this paper we present a significant extension of the SAT-sweeping algorithm that exploits local observability don't-cares (ODCs) to increase the number of vertices merged. We use a novel technique to bound the use of ODCs and thus the computational effort to find them, while still finding a large fraction of them. Our reported results based on a set of industrial benchmark circuits demonstrate that ODC-based SAT sweeping results in significantly more graph simplification with great benefit for Boolean reasoning with a moderate increase in computational effort.