Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
The use of observability and external don't cares for the simplification of multi-level networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Implicit enumeration of structural changes in circuit optimization
Proceedings of the 41st annual Design Automation Conference
SAT-Based Complete Don't-Care Computation for Network Optimization
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
FPGA technology mapping: a study of optimality
Proceedings of the 42nd annual Design Automation Conference
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
SAT sweeping with local observability don't-cares
Proceedings of the 43rd annual Design Automation Conference
Fixing Design Errors with Counterexamples and Resynthesis
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Node addition and removal in the presence of don't cares
Proceedings of the 47th Design Automation Conference
Global flow optimization in automatic logic design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Modern synthesis flows apply a series of technology independent optimization steps followed by mapping algorithms which bind the optimized network to a specific technology library. As the exact solution of the mapping problem is computationally intractable, algorithms used in practice use heuristic, typically tree-based approaches. The application of these algorithms results in mapped but suboptimal networks. In this work, we present a novel, efficient, and effective optimization algorithm for mapped networks which can be considered a generalization of SAT-sweeping. Our algorithm searches for alternative, more efficient implementations of each net in the network. Candidate support nets for reimplementation are selected using simulation signatures and verified using Boolean satisfiability. We report experimental results on the quality of our algorithm obtained from an implementation of the approach using the logic synthesis system ABC.