DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Chortle: a technology mapping program for lookup table-based field programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
On area/depth trade-off in LUT-based FPGA technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
RASP: a general logic synthesis system for SRAM-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
A new method to express functional permissibilities for LUT based FPGAs and its applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Cut ranking and pruning: enabling a general and efficient FPGA mapping solution
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Optimality study of logic synthesis for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Efficient SAT-based Boolean matching for FPGA technology mapping
Proceedings of the 43rd annual Design Automation Conference
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
How much can logic perturbation help from netlist to final routing for FPGAs
Proceedings of the 44th annual Design Automation Conference
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Incremental learning approach and SAT model for Boolean matching with don't cares
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
FPGA area reduction by multi-output function based sequential resynthesis
Proceedings of the 45th annual Design Automation Conference
Smart Enumeration: A Systematic Approach to Exhaustive Search
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
FPGA technology mapping with encoded libraries andstaged priority cuts
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
To SAT or not to SAT: Ashenhurst decomposition in a large scale
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Boolean factoring and decomposition of logic networks
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Robust FPGA resynthesis based on fault-tolerant Boolean matching
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Physical optimization for FPGAs using post-placement topology rewriting
Proceedings of the 2009 international symposium on Physical design
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
IPR: in-place reconfiguration for FPGA fault tolerance?
Proceedings of the 2009 International Conference on Computer-Aided Design
Building a faster boolean matcher using bloom filter
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the Conference on Design, Automation and Test in Europe
FPGA technology mapping with encoded libraries and staged priority cuts
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Engineering a scalable Boolean matching based on EDA SaaS 2.0
Proceedings of the International Conference on Computer-Aided Design
Generalized SAT-sweeping for post-mapping optimization
Proceedings of the 49th Annual Design Automation Conference
From design to design automation
Proceedings of the 2014 on International symposium on physical design
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This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small subcircuit into the smallest possible number of lookup tables (LUTs) needed to realize its functionality. We iteratively apply this technique to small portions of circuits that have already been technology mapped by the best available mapping algorithms for FPGAs. In many cases, the optimal mapping of the subcircuit uses fewer LUTs than is obtained by the technology mapping algorithm. We show that for some circuits the total area improvement can be up to 67%.