A survey of Boolean matching techniques for library binding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Boolean satisfiability in electronic design automation
Proceedings of the 37th Annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Technology mapping using boolean matching and don't care sets
EURO-DAC '90 Proceedings of the conference on European design automation
Symmetry detection for incompletely specified functions
Proceedings of the 41st annual Design Automation Conference
A new canonical form for fast boolean matching in logic synthesis and verification
Proceedings of the 42nd annual Design Automation Conference
FPGA technology mapping: a study of optimality
Proceedings of the 42nd annual Design Automation Conference
Efficient SAT-based Boolean matching for FPGA technology mapping
Proceedings of the 43rd annual Design Automation Conference
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Boolean matching for incompletely specified functions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improvements to Technology Mapping for LUT-Based FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithms for maximum satisfiability using unsatisfiable cores
Proceedings of the conference on Design, automation and test in Europe
Simulation and SAT-based Boolean matching for large Boolean networks
Proceedings of the 46th Annual Design Automation Conference
BooM: a decision procedure for boolean matching with abstraction and dynamic learning
Proceedings of the 47th Design Automation Conference
Boolean matching of function vectors with strengthened learning
Proceedings of the International Conference on Computer-Aided Design
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In this paper, we will propose an incremental learning approach to solve Boolean matching for incompletely specified functions. This approach can incrementally analyze current feasible partial mappings, detect and eliminate redundant manipulations in a proactive way. A new type of signature exploiting single variable symmetries is also given to reduce the searching space. Moreover, a SAT model of Boolean matching will be proposed to handle large Boolean functions. Through the utilization of these novel mechanisms, a drastic improvement on the performance of our Boolean matching algorithms are achieved. The experimental results demonstrate the effectiveness and efficiency of the proposed learning-based and SAT-based Boolean matching algorithms on many large benchmarking circuits.