DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
SOCRATES: a system for automatically synthesizing and optimizing combinational logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Logic synthesis for vlsi design
Logic synthesis for vlsi design
LSS: a system for production logic synthesis
IBM Journal of Research and Development
FPGA design principles (a tutorial)
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Technology mapping for electrically programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
BDDMAP: a technology mapper based on a new covering algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Boolean matching in logic synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Spectral transforms for large boolean functions with applications to technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
Boolean matching of sequential elements
DAC '94 Proceedings of the 31st annual Design Automation Conference
Boolean matching for incompletely specified functions
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient orthonormality testing for synthesis with pass-transistor selectors
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Combined spectral techniques for Boolean matching
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Library based technology mapping using multiple domain representations
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Hmap: a fast mapper for EPGAs using extended GBDD hash tables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Detection of symmetry of Boolean functions represented by ROBDDs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Boolean matching for large libraries
DAC '98 Proceedings of the 35th annual Design Automation Conference
Efficient Boolean function matching
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Least Upper Bounds for the Size of OBDDs Using Symmetry Properties
IEEE Transactions on Computers
Technology mapping for high-performance static CMOS and pass transistor logic designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Generalized symmetries in boolean functions
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Spectral Transforms for Large Boolean Functions withApplications to Technology Mapping
Formal Methods in System Design
IEEE Design & Test
Design reuse through high-level library mapping
EDTC '95 Proceedings of the 1995 European conference on Design and Test
An anytime symmetry detection algorithm for ROBDDs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fast Boolean Matching with Don't Cares
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Building a better Boolean matcher and symmetry detector
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Exploiting K-Distance Signature for Boolean Matching and G-Symmetry Detection
Proceedings of the 43rd annual Design Automation Conference
Incremental learning approach and SAT model for Boolean matching with don't cares
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Signature based Boolean matching in the presence of don't cares
Proceedings of the 45th annual Design Automation Conference
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We describe a new approach to technology mapping where matchings are recognized by means of Boolean operations. The matching algorithm uses tautology checking based on Shannon decompositions. We show how to use the symmetry and unateness properties to speed-up the Boolean matching algorithm. We examine how don't care information can be used during Boolean matching. The algorithms have been implemented in program Ceres and tested on the 1989 MCNC benchmark circuits.