Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Using if-then-else DAGs for multi-level logic minimization
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Logic synthesis for programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Technology mapping for electrically programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Amap: A technology mapper for selector-based field-programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Field-programmable gate arrays
Field-programmable gate arrays
An improved synthesis algorithm for multiplexor-based PGA's
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
MIM: logic module independent technology mapping for design and evaluation of antifuse-based FPGAs
DAC '93 Proceedings of the 30th international Design Automation Conference
SOCRATES: a system for automatically synthesizing and optimizing combinational logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Logic synthesis for vlsi design
Logic synthesis for vlsi design
Technology mapping using boolean matching and don't care sets
EURO-DAC '90 Proceedings of the conference on European design automation
A survey of Boolean matching techniques for library binding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A fast and efficient algorithm for technology mapping of electrically programmable gate arrays (EPGAs) is proposed. This Hmap algorithm covers the Boolean network with programmed logic modules bottom-up. The covering operation is based on collapsing the fanins of a node to form a bigger supernode such that fewer clusters are needed to be detected. Then Boolean matching is used to detect whether the collapsed supernode can be mapped into a logic module by looking up an extended GBDD hash table. The use of this table look-up matching can shorten the matching time significantly. As shown in the experiments, the average running time of Hmap is 20 times faster than that of MIS-pga2.