Technology mapping for electrically programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
LATTIS: an iterative speedup heuristic for mapped logic
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A near optimal algorithm for technology mapping minimizing area under delay constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Boolean matching in logic synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Automatic technology mapping for generalized fundamental-mode asynchronous designs
DAC '93 Proceedings of the 30th international Design Automation Conference
Surveys in combinatorics, 1993
Surveys in combinatorics, 1993
Espresso-signature: a new exact minimizer for logic functions
DAC '93 Proceedings of the 30th international Design Automation Conference
Low power state assignment targeting two-and multi-level logic implementations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Optimal latch mapping and retiming within a tree
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Decomposition methods for library binding of speed-independent asynchronous designs
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Boolean matching of sequential elements
DAC '94 Proceedings of the 31st annual Design Automation Conference
Logic extraction and factorization for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
New ideas for solving covering problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Logic clause analysis for delay optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Externally hazard-free implementations of asynchronous circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Two-level logic minimization for low power
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Series-parallel functions and FPGA logic module design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Universal logic modules for series-parallel functions
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Design of a logic synthesis system (tutorial)
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Delay minimal decomposition of multiplexers in technology mapping
DAC '96 Proceedings of the 33rd annual Design Automation Conference
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Integrated resynthesis for low power
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Hmap: a fast mapper for EPGAs using extended GBDD hash tables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low power multiplexer decomposition
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Solving covering problems using LPR-based lower bounds
DAC '97 Proceedings of the 34th annual Design Automation Conference
Trace driven logic synthesis—application to power minimization
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An exact solution to simultaneous technology mapping and linear placement problem
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1997 international symposium on Physical design
A new viewpoint on code generation for directed acyclic graphs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together
DAC '98 Proceedings of the 35th annual Design Automation Conference
On accelerating pattern matching for technology mapping
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Post-routing timing optimization with routing characterization
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Doing two-level logic minimization 100 times faster
Proceedings of the sixth annual ACM-SIAM symposium on Discrete algorithms
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Technology mapping for minimizing gate and routing area
Proceedings of the conference on Design, automation and test in Europe
A new structural pattern matching algorithm for technology mapping
Proceedings of the 38th annual Design Automation Conference
Processor modeling and code selection for retargetable compilation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Logic Synthesis and Verification
Multi-level logic optimization
Logic Synthesis and Verification
Logic Synthesis and Verification
Technology-based transformations
Logic Synthesis and Verification
BOOM: a heuristic boolean minimizer
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Genetic engineering versus natural evolution: genetic algorithms with deterministic operators
Journal of Systems Architecture: the EUROMICRO Journal
Optimizing average-case delay in technology mapping of burst-mode circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Improved technology mapping using a new approach to Boolean matching
EDTC '95 Proceedings of the 1995 European conference on Design and Test
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Technology mapping using boolean matching and don't care sets
EURO-DAC '90 Proceedings of the conference on European design automation
Advanced AI Search Techniques in Modern Digital Circuit Synthesis
Artificial Intelligence Review
Application-specific instruction generation for configurable processor architectures
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Effective bounding techniques for solving unate and binate covering problems
Proceedings of the 42nd annual Design Automation Conference
Factoring boolean functions using graph partitioning
Discrete Applied Mathematics - Special issue: Boolean and pseudo-boolean funtions
Statistical technology mapping for parametric yield
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Advanced AI search techniques in modern digital circuit synthesis
Artificial intelligence in logic design
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty
Proceedings of the 43rd annual Design Automation Conference
Performance-driven technology mapping with MSG partition and selective gate duplication
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Area minimization algorithm for parallel prefix adders under bitwise delay constraints
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
DDBDD: delay-driven BDD synthesis for FPGAs
Proceedings of the 44th annual Design Automation Conference
Algebraic Methods for Optimizing Constant Multiplications in Linear Systems
Journal of VLSI Signal Processing Systems
Area recovery under depth constraint by cut substitution for technology mapping for LUT-based FPGAs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Timing-driven N-way decomposition
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Factoring Boolean functions using graph partitioning
Discrete Applied Mathematics - Special issue: Boolean and pseudo-boolean funtions
Tri-based set operations and selective computation of prime implicates
ISMIS'11 Proceedings of the 19th international conference on Foundations of intelligent systems
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