Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Prime Implicants, Minimum Covers, and the Complexity of Logic Simplification
IEEE Transactions on Computers
Artificial Intelligence
Implicit and incremental computation of primes and essential primes of Boolean functions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Absolute Minimization of Completely Specified Switching Functions
IEEE Transactions on Computers
Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
A new viewpoint on two-level logic minimization
DAC '93 Proceedings of the 30th international Design Automation Conference
Proving circuit correctness using formal comparison between expected and extracted behaviour
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
An application of multiple-valued logic to a design of programmable logic arrays
MVL '78 Proceedings of the eighth international symposium on Multiple-valued logic
Logic synthesis for vlsi design
Logic synthesis for vlsi design
On a New Boolean Function with Applications
IEEE Transactions on Computers
Logic minimization using exclusive OR gates
Proceedings of the 38th annual Design Automation Conference
Ordered binary decision diagrams as knowledge-bases
Artificial Intelligence
Logic Synthesis and Verification
Translation among CNFs, characteristic models and ordered binary decision diagrams
Information Processing Letters
Ordered Binary Decision Diagrams as Knowledge-Bases
ISAAC '99 Proceedings of the 10th International Symposium on Algorithms and Computation
Reasoning with Ordered Binary Decision Diagrams
ISAAC '00 Proceedings of the 11th International Conference on Algorithms and Computation
Translation among CNFs, Characteristic Models and Ordered Binary Decision Diagrams
ISAAC '01 Proceedings of the 12th International Symposium on Algorithms and Computation
Synthesis of integer multipliers in sum of pseudoproducts form
Integration, the VLSI Journal
Dimension-reducible Boolean functions based on affine spaces
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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