Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables
IEEE Transactions on Computers
Absolute Minimization of Completely Specified Switching Functions
IEEE Transactions on Computers
On a New Boolean Function with Applications
IEEE Transactions on Computers
Technology Scaling Effects on Multipliers
IEEE Transactions on Computers
New Low-Complexity Bit-Parallel Finite Field Multipliers Using Weakly Dual Bases
IEEE Transactions on Computers
Doing two-level logic minimization 100 times faster
Proceedings of the sixth annual ACM-SIAM symposium on Discrete algorithms
An Effective Built-In Self-Test Scheme for Parallel Multipliers
IEEE Transactions on Computers
The Area-Time Complexity of Binary Multiplication
Journal of the ACM (JACM)
New Efficient Structure for a Modular Multiplier for RNS
IEEE Transactions on Computers
Logic minimization using exclusive OR gates
Proceedings of the 38th annual Design Automation Conference
Fast three-level logic minimization based on autosymmetry
Proceedings of the 39th annual Design Automation Conference
A New Design Technique for Column Compression Multipliers
IEEE Transactions on Computers
Low Complexity Multiplication in a Finite Field Using Ring Representation
IEEE Transactions on Computers
Three-level logic minimization based on function regularities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of SPP three-level logic networks using affine spaces
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Partial product reduction by using look-up tables for M×N multiplier
Integration, the VLSI Journal
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We discuss the realization of two standard multiplier structures in a three-level form based on EXOR, called sum of pseudoproducts (SPP for short). SPP extends the classical two-level sum of products form (SOP). Our study focuses on the minimization of the number of gates and levels of the circuits needed to construct Wallace-type multipliers, and a 54 × 54-bit multiplier. The basic building blocks explicitly studied are the 4 × 4 parallel multiply module, and the family of carry-save adders Ci, with i input lines, that compose the Wallace trees. We show that the ratio of the number of gates of Ci in SPP over SOP decreases exponentially with i, being very small even for small values of i (ratio 0.2 for i = 9). The evaluation of power, speed, and chip area with three different standard tools also shows the interest of the proposed approach.