Two-level logic minimization: an overview
Integration, the VLSI Journal
Synthesis of finite state machines: logic optimization
Synthesis of finite state machines: logic optimization
On a New Boolean Function with Applications
IEEE Transactions on Computers
Logic minimization using exclusive OR gates
Proceedings of the 38th annual Design Automation Conference
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Synthesis of integer multipliers in sum of pseudoproducts form
Integration, the VLSI Journal
Dimension-reducible Boolean functions based on affine spaces
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Sum of Pseudoproducts (SPP) is a three level logic synthesis technique developed in recent years. In this framework we exploit the "regularity" of Boolean functions to decrease minimization time. Our main results are: 1) the regularity of a Boolean function ƒ of n variables is expressed by its autosymmetry degree k (with 0 &xle; k &xle n), where k = 0 means no regularity (that is, we are not able to provide any advantage over standard synthesis); 2) for k &xge; 1 the function is autosymmetric, and a new function ƒk is identified in polynomial time; ƒk is "equivalent" to, but smaller than ƒ, and depends on n-k variables only; 3) given a minimal SPP form for ƒk a minimal SPP form for ƒ is built in linear time; 4) experimental results show that 61% of the functions in the classical Espresso benchmark suite are autosymmetric, and the SPP minimization time for them is critically reduced; we can also solve cases otherwise practically intractable. We finally discuss the role and meaning of autosymmetry.