Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables
IEEE Transactions on Computers
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Generalized Reed-Muller Forms as a Tool to Detect Symmetries
IEEE Transactions on Computers
Boolean Functions Classification via Fixed Polarity Reed-Muller Forms
IEEE Transactions on Computers
Doing two-level logic minimization 100 times faster
Proceedings of the sixth annual ACM-SIAM symposium on Discrete algorithms
Logic Synthesis and Optimization
Logic Synthesis and Optimization
Logic Design and Switching Theory
Logic Design and Switching Theory
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Logic minimization using exclusive OR gates
Proceedings of the 38th annual Design Automation Conference
Fast three-level logic minimization based on autosymmetry
Proceedings of the 39th annual Design Automation Conference
Synthesis of integer multipliers in sum of pseudoproducts form
Integration, the VLSI Journal
Majority-based reversible logic gates
Theoretical Computer Science
Efficient minimization of fully testable 2-SPP networks
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An approximation algorithm for fully testable kEP-SOP networks
Proceedings of the 17th ACM Great Lakes symposium on VLSI
The optimization of kEP-SOPs: Computational complexity, approximability and experiments
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the construction of small fully testable circuits with low depth
Microprocessors & Microsystems
A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Dimension-reducible Boolean functions based on affine spaces
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SOP restructuring by exploiting don't cares
Microprocessors & Microsystems
| Hi-index | 14.98 |
Consider a hypercube of $2^n$ points described by $n$ Boolean variables and a subcube of $2^m$ points, $m \leq n$. As is well-known, the Boolean function with value 1 in the points of the subcube can be expressed as the product (AND) of $n-m$ variables. The standard synthesis of arbitrary functions exploits this property. We extend the concept of subcube to the more powerful pseudocube. The basic set is still composed of $2^m$ points, but has a more general form. The function with value 1 in a pseudocube, called pseudoproduct, is expressed as the AND of $n-m$ EXOR-factors, each containing at most $m+1$ variables. Subcubes are special cases of pseudocubes and their corresponding pseudoproducts reduce to standard products. An arbitrary Boolean function can be expressed as a sum of pseudoproducts (SPP). This expression is in general much shorter than the standard sum of products, as demonstrated on some known benchmarks. The logical network of an $n$-bit adder is designed in SPP, as a relevant example of application of this new technique. A class of symmetric functions is also defined, particularly suitable for SPP representation.