IEEE Transactions on Computers - The MIT Press scientific computation series
Prime Implicants, Minimum Covers, and the Complexity of Logic Simplification
IEEE Transactions on Computers
Derivation of Minimal Sums for Completely Specified Functions
IEEE Transactions on Computers
Design of a simplified pipeline processor for floating point addition (SFPA)
ACM SIGSMALL/PC Notes
On the Size of PLAs Required to Realize Binary and Multiple-Valued Functions
IEEE Transactions on Computers
A New Approach to Realizing Partially Symmetric Functions
IEEE Transactions on Computers
The Transduction Method-Design of Logic Networks Based on Permissible Functions
IEEE Transactions on Computers
On the Complexity of Mod-2l Sum PLA's
IEEE Transactions on Computers
Timing optimization for multi-level combinational networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Absolute Minimization of Completely Specified Switching Functions
IEEE Transactions on Computers
HDL optimization using timed decision tables
DAC '96 Proceedings of the 33rd annual Design Automation Conference
On a New Boolean Function with Applications
IEEE Transactions on Computers
MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Worst and Best Irredundant Sum-of-Products Expressions
IEEE Transactions on Computers
Logic Synthesis and Verification
Minimization of AND-EXOR Expressions Using Rewrite Rules
IEEE Transactions on Computers
Overview of an Arithmetic Design System
DAC '81 Proceedings of the 18th Design Automation Conference
Test generation for programmable logic arrays
DAC '82 Proceedings of the 19th Design Automation Conference
Planar Multiple-Valued Decision Diagrams
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
Multiple-Valued Logic Design Using Multiple-Valued EXOR
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
On Input Permutation Technique for Multiple-Valued Logic Synthesis
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
Efficient computation of canonical form for Boolean matching in large libraries
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Minimization of memory size for heterogeneous MDDs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Proceedings of the 43rd annual Design Automation Conference
A Layout System for the Random Logic Portion of an MOS LSI Chip
IEEE Transactions on Computers
Logic Networks of Carry-Save Adders
IEEE Transactions on Computers
Input Variable Assignment and Output Phase Optimization of PLA's
IEEE Transactions on Computers
Residue Number System Truth-Table Look-Up Processing Moduli Selection and Logical Minimization
IEEE Transactions on Computers
Parallel Binary Adders with a Minimum Number of Connections
IEEE Transactions on Computers
A purely map procedure for two-level multiple-output logic minimization
International Journal of Computer Mathematics
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
TRECO: dynamic technology remapping for timing engineering change orders
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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