Logic testing and design for testability
Logic testing and design for testability
A Computer Algorithm for Minimizing Reed-Muller Canonical Forms
IEEE Transactions on Computers
On the Complexity of Mod-2l Sum PLA's
IEEE Transactions on Computers
A fast algorithm to minimize multi-output mixed-polarity generalized Reed-Muller forms
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Logic Design and Switching Theory
Logic Design and Switching Theory
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Testability of 2-Level AND/EXOR Circuits
Journal of Electronic Testing: Theory and Applications
Using PVM for Distributed Logic Minimization in a Network of Computers
Proceedings of the 6th European PVM/MPI Users' Group Meeting on Recent Advances in Parallel Virtual Machine and Message Passing Interface
Testability of 2-level AND/EXOR circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
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Conditions for generating optimal two-level AND-EXOR representations using rewrite rules are considered. Four results are presented. First, it is shown that a necessary condition for obtaining minimality is a temporary increase in the size of expressions during minimization. Second, a sufficient condition for obtaining minimality that consists of adding certain two rules to rule sets proposed in the literature is given. Third, transformations that allow the minimization of an expression to proceed by minimizing a transformed expression instead are defined. Fourth, it is determined experimentally that the above three theoretical results lead to better benchmarks results as well.