Computer Logic, Testing and Verification
Computer Logic, Testing and Verification
A Method for Modulo-2 Minimization
IEEE Transactions on Computers - Lecture notes in computer science Vol. 174
Exclusive-OR representations of Boolean functions
IBM Journal of Research and Development
On the Complexity of Mod-2l Sum PLA's
IEEE Transactions on Computers
A graph-based synthesis algorithm for AND/XOR networks
DAC '97 Proceedings of the 34th annual Design Automation Conference
A fast algorithm to minimize multi-output mixed-polarity generalized Reed-Muller forms
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Minimization of AND-EXOR Expressions Using Rewrite Rules
IEEE Transactions on Computers
Minimizing AND-EXOR Expressions for Multiple-Valued Two-Input Logic Functions
TAMC '09 Proceedings of the 6th Annual Conference on Theory and Applications of Models of Computation
Secure computations in a minimal model using multiple-valued ESOP expressions
TAMC'06 Proceedings of the Third international conference on Theory and Applications of Models of Computation
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A computer algorithm is presented that uses geometrical operations to minimize multioutput Reed-Muller expansions of up to ten variables.