A Computer Algorithm for Minimizing Reed-Muller Canonical Forms
IEEE Transactions on Computers
A fast algorithm to minimize multi-output mixed-polarity generalized Reed-Muller forms
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Logic Design and Switching Theory
Logic Design and Switching Theory
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Boolean Matrix Transforms for the Minimization of Modulo-2 Canonical Expansions
IEEE Transactions on Computers
DAC '94 Proceedings of the 31st annual Design Automation Conference
Fast OFDD based minimization of fixed polarity Reed-Muller expressions
EURO-DAC '94 Proceedings of the conference on European design automation
LOT: logic optimization with testability—new transformations using recursive learning
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computers
Generalized Partially-Mixed-Polarity Reed-Muller Expansion and Its Fast Computation
IEEE Transactions on Computers
Fast OFDD-Based Minimization of Fixed Polarity Reed-Muller Expressions
IEEE Transactions on Computers
Boolean Functions Classification via Fixed Polarity Reed-Muller Forms
IEEE Transactions on Computers
Easily Testable Realizations for Generalized Reed-Muller Expressions
IEEE Transactions on Computers
Easily Testable Multiple-Valued Logic Circuits Derived from Reed-Muller Circuits
IEEE Transactions on Computers
Cybernetics and Systems Analysis
Minimization of AND-EXOR Expressions Using Rewrite Rules
IEEE Transactions on Computers
A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions
IEEE Transactions on Computers
Efficient Decomposition Techniques for FPGAs
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Efficient Realization of Parity Prediction Functions in FPGAs
Journal of Electronic Testing: Theory and Applications
Area Minimization of Exclusive-OR Intensive Circuits in FPGAs
Journal of Electronic Testing: Theory and Applications
Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Novel synthesis and optimization of multi-level mixed polarity Reed-Muller functions
Journal of Computer Science and Technology
Optimal polarity for dual Reed-Muller expressions
MINO'08 Proceedings of the 7th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronics
Minimization of OR-XNOR expressions using four new linking rules
AIKED'08 Proceedings of the 7th WSEAS International Conference on Artificial intelligence, knowledge engineering and data bases
Minimizing AND-EXOR Expressions for Multiple-Valued Two-Input Logic Functions
TAMC '09 Proceedings of the 6th Annual Conference on Theory and Applications of Models of Computation
Synthesis of multi-level dual reed-muller expressions
NANOTECHNOLOGY'09 Proceedings of the 1st WSEAS international conference on Nanotechnology
Fast coding for dual Reed-Muller expressions
EDUCATION'09 Proceedings of the 6th WSEAS international conference on Engineering education
Boolean rings for intersection-based satisfiability
LPAR'06 Proceedings of the 13th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Secure computations in a minimal model using multiple-valued ESOP expressions
TAMC'06 Proceedings of the Third international conference on Theory and Applications of Models of Computation
Exact ESOP expressions for incompletely specified functions
Integration, the VLSI Journal
| Hi-index | 15.01 |
Consideration is given to the realization of logic functions by using PLAs with an exclusive-OR (EXOR) array, where a function is represented by mod-2 (EXOR) sum-of-products (ESOPs) and both true and complemented variables are used. The authors propose a new PLA structure using an EXOR array. They derive upper bounds on the number of products of this type of PLA that are useful for estimating the size of a PLA as well as for assessing the minimality of the solutions obtained by heuristic ESOP minimization algorithms. Computer simulation using randomly generated functions shows that PLAs with the EXOR array require, on the average, fewer products than conventional PLAs. For symmetric functions, the authors conjecture that the PLAs with an EXOR array require, at most, as many products as the conventional PLAs. The proposed PLAs can be made easily testable by adding a small amount of hardware.