Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
On the Complexity of Mod-2l Sum PLA's
IEEE Transactions on Computers
Easily Testable Realizations for Generalized Reed-Muller Expressions
IEEE Transactions on Computers
A Method for Modulo-2 Minimization
IEEE Transactions on Computers - Lecture notes in computer science Vol. 174
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of multi-level dual reed-muller expressions
NANOTECHNOLOGY'09 Proceedings of the 1st WSEAS international conference on Nanotechnology
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This paper presents a minimization algorithm for fixed polarity dual Reed-Muller expressions (FPDRMs) for completely specified functions. For an n-variable function there are 2n different distinct FPDRMs. Minimum FPDRMs is one with the fewest number of sums. The minimization algorithm for the two-level dual Reed-Muller expressions has been developed, based on a four set of rules. The four new linking rules have been introduced to minimize single output dual Reed-Muller (OR/XNOR) expressions. The new rules are demonstrated using Karnaugh maps for some random functions.