Logic testing and design for testability
Logic testing and design for testability
Fault Detection in Combinational Networks by Reed-Muller Transforms
IEEE Transactions on Computers
On the Complexity of Mod-2l Sum PLA's
IEEE Transactions on Computers
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Logic Synthesis and Optimization
Logic Synthesis and Optimization
Modern Logic Design
Representations of Discrete Functions
Representations of Discrete Functions
Fast Minimization of Mixed-Polarity AND/XOR Canonical Networks
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits
IEEE Transactions on Computers
Easily Testable Multiple-Valued Logic Circuits Derived from Reed-Muller Circuits
IEEE Transactions on Computers
Automation and Remote Control
Bridging Fault Detections for Testable Realizations of Logic Functions
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal polarity for dual Reed-Muller expressions
EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Optimal polarity for dual Reed-Muller expressions
EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Optimal polarity for dual Reed-Muller expressions
MINO'08 Proceedings of the 7th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronics
Minimization of OR-XNOR expressions using four new linking rules
AIKED'08 Proceedings of the 7th WSEAS International Conference on Artificial intelligence, knowledge engineering and data bases
Synthesis of multi-level dual reed-muller expressions
NANOTECHNOLOGY'09 Proceedings of the 1st WSEAS international conference on Nanotechnology
Testable design of AND-EXOR logic networks with universal test sets
Computers and Electrical Engineering
Fast coding for dual Reed-Muller expressions
EDUCATION'09 Proceedings of the 6th WSEAS international conference on Engineering education
Exact minimization of dual Reed-Muller expansions
ACS'06 Proceedings of the 6th WSEAS international conference on Applied computer science
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This paper presents a design method of easily testable AND-EXOR networks. It is an improvement of Reddy and Saluja-Reddy's methods, and has the following features: 1) The network uses generalized Reed-Muller expressions (GRMs) instead of Positive Polarity Reed-Muller expressions (PPRMs). The average number of products for GRMs is less than half of that for PPRMs, and is less than that of sum-of-products expressions (SOPs). 2) The network consists of a literal part, an AND part, an EXOR part, and a check part. 3) The EXOR part can be a tree instead of a cascade. Thus, the network is faster. 4) The test detects multiple stuck at faults under the assumption that the faults occur at most one part, either the literal part, the AND part, the EXOR part, or the check part.