Logic testing and design for testability
Logic testing and design for testability
On the Complexity of Mod-2l Sum PLA's
IEEE Transactions on Computers
Generalized Partially-Mixed-Polarity Reed-Muller Expansion and Its Fast Computation
IEEE Transactions on Computers
Easily Testable Realizations for Generalized Reed-Muller Expressions
IEEE Transactions on Computers
A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits
IEEE Transactions on Computers
Testability of 2-Level AND/EXOR Circuits
Journal of Electronic Testing: Theory and Applications
Logic minimization using exclusive OR gates
Proceedings of the 38th annual Design Automation Conference
Logic Synthesis and Optimization
Logic Synthesis and Optimization
Bridging Fault Detections for Testable Realizations of Logic Functions
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
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Testable design for detecting stuck-at and bridging faults in Programmable Logic Arrays (PLAs) based on Double Fixed-Polarity Reed-Muller Expression (DFPRM) is proposed. DFPRMs are generalized expressions of FPRM. It has advantages of compactness and easy testability. The EXOR part in the proposed design is implemented with tree structure that admits a universal test set. For an n-variable function, this design can be tested by (2n+8) test vectors, which are independent of the function and the circuit-under-test (CUT). Excepting a few intergate bridging faults in the EXOR-tree, it detects all other single bridging (both OR-and AND-type) and all single stuck-at faults. This tree based implementation reduces circuit delay significantly compared to cascaded EXOR-part.