A method for generating weighted random test pattern
IBM Journal of Research and Development
The random testability of the n-input AND gate
STACS 91 Proceedings of the 8th annual symposium on Theoretical aspects of computer science
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Fast OFDD based minimization of fixed polarity Reed-Muller expressions
EURO-DAC '94 Proceedings of the conference on European design automation
Test Routines Based on Symbolic Logical Statements
Journal of the ACM (JACM)
Logic Synthesis and Optimization
Logic Synthesis and Optimization
Concrete Math
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Minimization of AND-EXOR Expressions Using Rewrite Rules
IEEE Transactions on Computers
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Automated Logic Synthesis of Random-Pattern-Testable Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Testable design of AND-EXOR logic networks with universal test sets
Computers and Electrical Engineering
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It is often stated that AND/EXOR circuits are much easier to test than AND/OR circuits. This statement, however, only holds true for circuits derived from restricted classes of AND/EXOR expressions, like positive polarity Reed-Muller and fixed polarity Reed-Muller expressions. For these two classes of expressions, circuits with good deterministic testability properties are known. In this paper we show that these circuits also have good random pattern testability attributes. An input probability distribution is given that yields a short expected test length for biased random patterns. This is the first time theoretical results on random pattern testability are presented for 2-level AND/EXOR circuit realizations of arbitrary Boolean functions. It turns out that analogous results cannot be expected for less restricted classes of 2-level AND/EXOR circuits. We present experiments demonstrating that generally minimized 2-level AND/OR circuits can be tested as easy (or hard) as minimized 2-level AND/EXOR circuits.