Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
On the Complexity of Mod-2l Sum PLA's
IEEE Transactions on Computers
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Field-programmable gate arrays
Field-programmable gate arrays
Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
Reduction of OBDDs in linear time
Information Processing Letters
Boolean matching using generalized Reed-Muller forms
DAC '94 Proceedings of the 31st annual Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
Logic Synthesis and Optimization
Logic Synthesis and Optimization
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Fast Minimization of Mixed-Polarity AND/XOR Canonical Networks
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
On the Expressive Power of OKFDDs
Formal Methods in System Design
A graph-based synthesis algorithm for AND/XOR networks
DAC '97 Proceedings of the 34th annual Design Automation Conference
On Variable Ordering and Decomposition Type Choice in OKFDDs
IEEE Transactions on Computers
Testability of 2-Level AND/EXOR Circuits
Journal of Electronic Testing: Theory and Applications
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
Heuristic Learning Based on Genetic Programming
Genetic Programming and Evolvable Machines
Verifying integrity of decision diagrams
Integration, the VLSI Journal
Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions
EDTC '95 Proceedings of the 1995 European conference on Design and Test
How many decomposition types do we need? [decision diagrams]
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Testability of 2-level AND/EXOR circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Decision Diagrams in Synthesis - Algorithms, Applications and Extensions
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A genetic algorithm for decomposition type choice in OKFDDs
INBS '95 Proceedings of the First International Symposium on Intelligence in Neural and Biological Systems (INBS'95)
Evolutionary Synthesis of LogicCircuits Using Information Theory
Artificial Intelligence Review
TED+: a data structure for microprocessor verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Synthesizing complementary circuits automatically
Proceedings of the 2009 International Conference on Computer-Aided Design
Synthesizing complementary circuits automatically
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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