On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Fast OFDD based minimization of fixed polarity Reed-Muller expressions
EURO-DAC '94 Proceedings of the conference on European design automation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Low power logic synthesis for XOR based circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Synthesis of Communicating Processes from Temporal Logic Specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Automata on Infinite Objects and Church's Problem
Automata on Infinite Objects and Church's Problem
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Deterministic generators and games for Ltl fragments
ACM Transactions on Computational Logic (TOCL)
A SAT-based algorithm for reparameterization in symbolic simulation
Proceedings of the 41st annual Design Automation Conference
Prime clauses for fast enumeration of satisfying assignments to boolean circuits
Proceedings of the 42nd annual Design Automation Conference
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
On synthesizing controllers from bounded-response properties
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Minimizing counterexample with unit core extraction and incremental SAT
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
Efficient conflict analysis for finding all satisfying assignments of a boolean circuit
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
A new algorithm for strategy synthesis in LTL games
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Synthesis of reactive(1) designs
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
Synthesizing complementary circuits automatically
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A halting algorithm to determine the existence of decoder
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Inferring assertion for complementary synthesis
Proceedings of the International Conference on Computer-Aided Design
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One of the most difficult jobs in designing communication and multimedia chips, is to design and verify complex complementary circuit pair (E, E-1), in which circuit E transforms information into a format that is suitable for transmission and storage, while E's complementary circuit E-1 recovers this information. In order to ease this job, we propose a novel two-step approach to synthesize complementary circuit E-1 from E fully automatically. First, we assume that the circuit E satisfies parameterized complementary assumption, which means its input can be recovered from its output under some parameter setting. We check this assumption with SAT solver and find out proper values of these parameters. Second, with parameter values and the SAT instance obtained in the first step, we build the complementary circuit E-1 with an efficient satisfying assignments enumeration technique that is specially designed for circuits with lots of XOR gates. To illustrate its usefulness and efficiency, we run our algorithm on several complex encoders from industrial projects, including PCIE and 10G ethernet, and successfully generate correct complementary circuits for them.