Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Synthesis of Communicating Processes from Temporal Logic Specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Verification by augmented finitary abstraction
Information and Computation
Automata on Infinite Objects and Church's Problem
Automata on Infinite Objects and Church's Problem
On the Synthesis of an Asynchronous Reactive Module
ICALP '89 Proceedings of the 16th International Colloquium on Automata, Languages and Programming
The ForSpec Temporal Logic: A New Temporal Property-Specification Language
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
A Platform for Combining Deductive with Algorithmic Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Deterministic generators and games for Ltl fragments
ACM Transactions on Computational Logic (TOCL)
Distributed reactive systems are hard to synthesize
SFCS '90 Proceedings of the 31st Annual Symposium on Foundations of Computer Science
Bridging the gap between fair simulation and trace inclusion
Information and Computation
Interactive presentation: Automatic hardware synthesis from specifications: a case study
Proceedings of the conference on Design, automation and test in Europe
Synthesizing reactive systems from LSC requirements using the play-engine
Companion to the 22nd ACM SIGPLAN conference on Object-oriented programming systems and applications companion
Specify, Compile, Run: Hardware from PSL
Electronic Notes in Theoretical Computer Science (ENTCS)
Maintenance goals of agents in a dynamic environment: Formulation and policy construction
Artificial Intelligence
Dealing with Nondeterminism in Symbolic Control
HSCC '08 Proceedings of the 11th international workshop on Hybrid Systems: Computation and Control
ICALP '08 Proceedings of the 35th international colloquium on Automata, Languages and Programming, Part II
LTL Generalized Model Checking Revisited
VMCAI '09 Proceedings of the 10th International Conference on Verification, Model Checking, and Abstract Interpretation
Compositional Synthesis of Reactive Systems from Live Sequence Chart Specifications
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
Controller Synthesis from LSC Requirements
FASE '09 Proceedings of the 12th International Conference on Fundamental Approaches to Software Engineering: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009
Synthesizing complementary circuits automatically
Proceedings of the 2009 International Conference on Computer-Aided Design
Automatic deployment of autonomous cars in a robotic urban-like environment (rule)
ICRA'09 Proceedings of the 2009 IEEE international conference on Robotics and Automation
Automated composition of Web services via planning in asynchronous domains
Artificial Intelligence
Synthesis of programs from temporal property specifications
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Receding horizon control for temporal logic specifications
Proceedings of the 13th ACM international conference on Hybrid systems: computation and control
On synthesizing controllers from bounded-response properties
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Anzu: a tool for property synthesis
CAV'07 Proceedings of the 19th international conference on Computer aided verification
RAT: a tool for the formal analysis of requirements
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Automatic deployment of distributed teams of robots from temporal logic motion specifications
IEEE Transactions on Robotics
Diagnostic information for realizability
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
A hybrid algorithm for LTL games
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
PLDI '10 Proceedings of the 2010 ACM SIGPLAN conference on Programming language design and implementation
Agent programming via planning programs
Proceedings of the 9th International Conference on Autonomous Agents and Multiagent Systems: volume 1 - Volume 1
Agent composition synthesis based on ATL
Proceedings of the 9th International Conference on Autonomous Agents and Multiagent Systems: volume 1 - Volume 1
Automated composition of nondeterministic stateful services
WS-FM'09 Proceedings of the 6th international conference on Web services and formal methods
Synthesis of live behaviour models
Proceedings of the eighteenth ACM SIGSOFT international symposium on Foundations of software engineering
Synthesis of trigger properties
LPAR'10 Proceedings of the 16th international conference on Logic for programming, artificial intelligence, and reasoning
AspectLTL: an aspect language for LTL specifications
Proceedings of the tenth international conference on Aspect-oriented software development
TuLiP: a software toolbox for receding horizon temporal logic planning
Proceedings of the 14th international conference on Hybrid systems: computation and control
Synthesis of live behaviour models for fallible domains
Proceedings of the 33rd International Conference on Software Engineering
Generalized rabin(1) synthesis with applications to robust system synthesis
NFM'11 Proceedings of the Third international conference on NASA Formal methods
Debugging unrealizable specifications with model-based diagnosis
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Revisiting synthesis of GR(1) specifications
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
A halting algorithm to determine the existence of decoder
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Synthesis for regular specifications over unbounded domains
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Does it pay to extend the perimeter of a world model?
FM'11 Proceedings of the 17th international conference on Formal methods
ADDiff: semantic differencing for activity diagrams
Proceedings of the 19th ACM SIGSOFT symposium and the 13th European conference on Foundations of software engineering
Analyzing unsynthesizable specifications for high-level robot behavior using LTLMoP
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Beyond QCSP for solving control problems
CP'11 Proceedings of the 17th international conference on Principles and practice of constraint programming
Antichains and compositional algorithms for LTL synthesis
Formal Methods in System Design
JTLV: a framework for developing verification algorithms
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Robustness in the presence of liveness
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
RATSY – a new requirements analysis tool with synthesis
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Synthesis of Reactive(1) designs
Journal of Computer and System Sciences
Synthesis from scenario-based specifications
Journal of Computer and System Sciences
Two-way traceability and conflict debugging for AspectLTL programs
Proceedings of the 11th annual international conference on Aspect-oriented Software Development
Minimising deterministic Büchi automata precisely using SAT solving
SAT'10 Proceedings of the 13th international conference on Theory and Applications of Satisfiability Testing
On synthesizing robust discrete controllers under modeling uncertainty
Proceedings of the 15th ACM international conference on Hybrid Systems: Computation and Control
Recent challenges and ideas in temporal synthesis
SOFSEM'12 Proceedings of the 38th international conference on Current Trends in Theory and Practice of Computer Science
Effective synthesis of asynchronous systems from GR(1) specifications
VMCAI'12 Proceedings of the 13th international conference on Verification, Model Checking, and Abstract Interpretation
Towards a notion of unsatisfiable and unrealizable cores for LTL
Science of Computer Programming
Formal Methods in System Design
Sciduction: combining induction, deduction, and structure for verification and synthesis
Proceedings of the 49th Annual Design Automation Conference
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Deterministic automata for the (f, g)-fragment of LTL
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
MGSyn: automatic synthesis for industrial automation
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Translating to Co-Büchi Made Tight, Unified, and Useful
ACM Transactions on Computational Logic (TOCL)
Synthesis from incompatible specifications
Proceedings of the tenth ACM international conference on Embedded software
Assume-guarantee scenarios: semantics and synthesis
MODELS'12 Proceedings of the 15th international conference on Model Driven Engineering Languages and Systems
ATVA'12 Proceedings of the 10th international conference on Automated Technology for Verification and Analysis
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
Generalized reactivity(1) synthesis without a monolithic strategy
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
Synthesizing nonanomalous event-based controllers for liveness goals
ACM Transactions on Software Engineering and Methodology (TOSEM)
Automatic behavior composition synthesis
Artificial Intelligence
Proceedings of the 16th international conference on Hybrid systems: computation and control
Temporal logic model predictive control for discrete-time systems
Proceedings of the 16th international conference on Hybrid systems: computation and control
Example-driven modeling: model = abstractions + examples
Proceedings of the 2013 International Conference on Software Engineering
Controller synthesis: from modelling to enactment
Proceedings of the 2013 International Conference on Software Engineering
Synthesis modulo recursive functions
Proceedings of the 2013 ACM SIGPLAN international conference on Object oriented programming systems languages & applications
Automata with generalized rabin pairs for probabilistic model checking and LTL synthesis
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
Verification and synthesis in description logic based dynamic systems
RR'13 Proceedings of the 7th international conference on Web Reasoning and Rule Systems
A constraint-based approach to solving games on infinite graphs
Proceedings of the 41st ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages
Two-Way traceability and conflict debugging for AspectLTL programs
Transactions on Aspect-Oriented Software Development X
Supporting incremental behaviour model elaboration
Computer Science - Research and Development
Supporting incremental behaviour model elaboration
Computer Science - Research and Development
Concurrency control generation for dynamic threads using discrete-event systems
Science of Computer Programming
LTL receding horizon control for finite deterministic systems
Automatica (Journal of IFAC)
Synthesis of hierarchical systems
Science of Computer Programming
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We consider the problem of synthesizing digital designs from their ltl specification. In spite of the theoretical double exponential lower bound for the general case, we show that for many expressive specifications of hardware designs the problem can be solved in time N3, where N is the size of the state space of the design. We describe the context of the problem, as part of the Prosyd European Project which aims to provide a property-based development flow for hardware designs. Within this project, synthesis plays an important role, first in order to check whether a given specification is realizable, and then for synthesizing part of the developed system.