On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
A hierarchy of temporal properties (invited paper, 1989)
PODC '90 Proceedings of the ninth annual ACM symposium on Principles of distributed computing
Safety and liveness from a methodological point of view
Information Processing Letters
In transition from global to modular temporal reasoning about programs
Logics and models of concurrent systems
The existence of refinement mappings
Theoretical Computer Science
Preserving liveness: comments on “safety and liveness from a methodological point of view”
Information Processing Letters
Reducing BDD size by exploiting functional dependencies
DAC '93 Proceedings of the 30th international Design Automation Conference
Synthesis of Communicating Processes from Temporal Logic Specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Verification by augmented finitary abstraction
Information and Computation
Automata on Infinite Objects and Church's Problem
Automata on Infinite Objects and Church's Problem
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Realizable and Unrealizable Specifications of Reactive Systems
ICALP '89 Proceedings of the 16th International Colloquium on Automata, Languages and Programming
On the Synthesis of an Asynchronous Reactive Module
ICALP '89 Proceedings of the 16th International Colloquium on Automata, Languages and Programming
Small Progress Measures for Solving Parity Games
STACS '00 Proceedings of the 17th Annual Symposium on Theoretical Aspects of Computer Science
Building Circuits from Relations
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
An Improved Algorithm for the Evaluation of Fixpoint Expressions
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
A Platform for Combining Deductive with Algorithmic Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Algorithmic Verification of Linear Temporal Logic Specifications
ICALP '98 Proceedings of the 25th International Colloquium on Automata, Languages and Programming
Deterministic generators and games for Ltl fragments
ACM Transactions on Computational Logic (TOCL)
FOCS '05 Proceedings of the 46th Annual IEEE Symposium on Foundations of Computer Science
An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps
Formal Methods in System Design
Formal analysis of hardware requirements
Proceedings of the 43rd annual Design Automation Conference
Optimizations for LTL Synthesis
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
Interactive presentation: Automatic hardware synthesis from specifications: a case study
Proceedings of the conference on Design, automation and test in Europe
Specify, Compile, Run: Hardware from PSL
Electronic Notes in Theoretical Computer Science (ENTCS)
Distributed reactive systems are hard to synthesize
SFCS '90 Proceedings of the 31st Annual Symposium on Foundations of Computer Science
On the Merits of Temporal Testers
25 Years of Model Checking
Environment Assumptions for Synthesis
CONCUR '08 Proceedings of the 19th international conference on Concurrency Theory
Compositional Synthesis of Reactive Systems from Live Sequence Chart Specifications
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
Controller Synthesis from LSC Requirements
FASE '09 Proceedings of the 12th International Conference on Fundamental Approaches to Software Engineering: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009
Better Quality in Synthesis through Quantitative Objectives
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
An Antichain Algorithm for LTL Realizability
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Bridging the gap between fair simulation and trace inclusion
Information and Computation
Synthesis of programs from temporal property specifications
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Receding horizon control for temporal logic specifications
Proceedings of the 13th ACM international conference on Hybrid systems: computation and control
Symbolic synthesis of finite-state controllers for request-response specifications
CIAA'03 Proceedings of the 8th international conference on Implementation and application of automata
Anzu: a tool for property synthesis
CAV'07 Proceedings of the 19th international conference on Computer aided verification
RAT: a tool for the formal analysis of requirements
CAV'07 Proceedings of the 19th international conference on Computer aided verification
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Diagnostic information for realizability
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
A hybrid algorithm for LTL games
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
AspectLTL: an aspect language for LTL specifications
Proceedings of the tenth international conference on Aspect-oriented software development
Solving games without determinization
CSL'06 Proceedings of the 20th international conference on Computer Science Logic
Safraless compositional synthesis
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Minimizing generalized büchi automata
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
A new algorithm for strategy synthesis in LTL games
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
JTLV: a framework for developing verification algorithms
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Robustness in the presence of liveness
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
RATSY – a new requirements analysis tool with synthesis
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Synthesis of reactive(1) designs
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
On synthesizing robust discrete controllers under modeling uncertainty
Proceedings of the 15th ACM international conference on Hybrid Systems: Computation and Control
Synthesis for unbounded bit-vector arithmetic
IJCAR'12 Proceedings of the 6th international joint conference on Automated Reasoning
The quest for runware: on compositional, executable and intuitive models
Software and Systems Modeling (SoSyM)
Assume-guarantee scenarios: semantics and synthesis
MODELS'12 Proceedings of the 15th international conference on Model Driven Engineering Languages and Systems
Qualitative approximate behavior composition
JELIA'12 Proceedings of the 13th European conference on Logics in Artificial Intelligence
Code aware resource management
Formal Methods in System Design
Counter play-out: executing unrealizable scenario-based specifications
Proceedings of the 2013 International Conference on Software Engineering
Fair LTL synthesis for non-deterministic systems using strong cyclic planners
IJCAI'13 Proceedings of the Twenty-Third international joint conference on Artificial Intelligence
Two-Way traceability and conflict debugging for AspectLTL programs
Transactions on Aspect-Oriented Software Development X
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We address the problem of automatically synthesizing digital designs from linear-time specifications. We consider various classes of specifications that can be synthesized with effort quadratic in the number of states of the reactive system, where we measure effort in symbolic steps. The synthesis algorithm is based on a novel type of game called General Reactivity of rank 1 (gr(1)), with a winning condition of the form(@?@?@?p"1@?...@?@?@?@?p"m)-(@?@?@?q"1@?...@?@?@?@?q"n), where each p"i and q"i is a Boolean combination of atomic propositions. We show symbolic algorithms to solve this game, to build a winning strategy and several ways to optimize the winning strategy and to extract a system from it. We also show how to use gr(1) games to solve the synthesis of ltl specifications in many interesting cases. As empirical evidence to the generality and efficiency of our approach we include a significant case study. We describe the formal specifications and the synthesis process applied to a bus arbiter, which is a realistic industrial hardware specification of modest size.