On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Reducing BDD size by exploiting functional dependencies
DAC '93 Proceedings of the 30th international Design Automation Conference
Automata on Infinite Objects and Church's Problem
Automata on Infinite Objects and Church's Problem
Efficient Büchi Automata from LTL Formulae
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Building Circuits from Relations
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Freedom, Weakness, and Determinism: From Linear-Time to Branching-Time
LICS '98 Proceedings of the 13th Annual IEEE Symposium on Logic in Computer Science
The common fragment of CTL and LTL
FOCS '00 Proceedings of the 41st Annual Symposium on Foundations of Computer Science
Deterministic generators and games for Ltl fragments
ACM Transactions on Computational Logic (TOCL)
Formal analysis of hardware requirements
Proceedings of the 43rd annual Design Automation Conference
Optimizations for LTL Synthesis
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
Interactive presentation: Automatic hardware synthesis from specifications: a case study
Proceedings of the conference on Design, automation and test in Europe
Symbolic synthesis of finite-state controllers for request-response specifications
CIAA'03 Proceedings of the 8th international conference on Implementation and application of automata
A new algorithm for strategy synthesis in LTL games
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Synthesis of reactive(1) designs
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
ICALP '08 Proceedings of the 35th international colloquium on Automata, Languages and Programming, Part II
A hybrid algorithm for LTL games
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
Compositional algorithms for LTL synthesis
ATVA'10 Proceedings of the 8th international conference on Automated technology for verification and analysis
Making the right cut in model checking data-intensive timed systems
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
AspectLTL: an aspect language for LTL specifications
Proceedings of the tenth international conference on Aspect-oriented software development
Generalized rabin(1) synthesis with applications to robust system synthesis
NFM'11 Proceedings of the Third international conference on NASA Formal methods
Debugging unrealizable specifications with model-based diagnosis
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Revisiting synthesis of GR(1) specifications
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Unbeast: symbolic bounded synthesis
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Program sketching via CTL* model checking
Proceedings of the 18th international SPIN conference on Model checking software
Small strategies for safety games
ATVA'11 Proceedings of the 9th international conference on Automated technology for verification and analysis
Evaluating LTL satisfiability solvers
ATVA'11 Proceedings of the 9th international conference on Automated technology for verification and analysis
Antichains and compositional algorithms for LTL synthesis
Formal Methods in System Design
Journal of Computer and System Sciences
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
PESSOA: a tool for embedded controller synthesis
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Synthesis of Reactive(1) designs
Journal of Computer and System Sciences
Minimising deterministic Büchi automata precisely using SAT solving
SAT'10 Proceedings of the 13th international conference on Theory and Applications of Satisfiability Testing
VMCAI'12 Proceedings of the 13th international conference on Verification, Model Checking, and Abstract Interpretation
Towards a notion of unsatisfiable and unrealizable cores for LTL
Science of Computer Programming
Formal Methods in System Design
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Strategy machines and their complexity
MFCS'12 Proceedings of the 37th international conference on Mathematical Foundations of Computer Science
Generalized reactivity(1) synthesis without a monolithic strategy
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
PARTY: parameterized synthesis of token rings
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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We propose to use a formal specification language as a high-level hardware description language. Formal languages allow for compact, unambiguous representations and yield designs that are correct by construction. The idea of automatic synthesis from specifications is old, but used to be completely impractical. Recently, great strides towards efficient synthesis from specifications have been made. In this paper we extend these recent methods to generate compact circuits and we show their practicality by synthesizing a generalized buffer and an arbiter for ARM's AMBA AHB bus from specifications given in PSL. These are the first industrial examples that have been synthesized automatically from their specifications.