Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Theoretical Computer Science
Timing Assumptions and Verification of Finite-State Concurrent Systems
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Improvements in BDD-Based Reachability Analysis of Timed Automata
FME '01 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods for Increasing Software Productivity
Efficient Timed Reachability Analysis Using Clock Difference Diagrams
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Verification of Real-Time Systems by Successive Over and Under Approximation
Proceedings of the 7th International Conference on Computer Aided Verification
Some Progress in the Symbolic Verification of Timed Automata
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Efficient verification of timed automata with BDD-like data structures
International Journal on Software Tools for Technology Transfer (STTT)
Development and evaluation of symbolic model checker based on approximation for real-time systems
Systems and Computers in Japan
Towards the Formal Verification of Lower System Layers in Automotive Systems
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Advanced Unbounded Model Checking Based on AIGs, BDD Sweeping, And Quantifier Scheduling
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Specify, Compile, Run: Hardware from PSL
Electronic Notes in Theoretical Computer Science (ENTCS)
Principles of Model Checking (Representation and Mind Series)
Principles of Model Checking (Representation and Mind Series)
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The success of industrial-scale model checkers such as UPPAAL [3] or NUSMV [12] relies on the efficiency of their respective symbolic state space representations. While difference bound matrices (DBMs) are effective for representing sets of clock values, binary decision diagrams (BDDs) can efficiently represent huge discrete state sets. In this paper, we introduce a simple general framework for combining both data structures, enabling a joint symbolic representation of the timed state sets in the reachability fixed point construction. In contrast to other approaches, our technique is robust against intricate interdependencies between clock constraints and the location information. Especially in the analysis of models with only few clocks, large constants, and a huge discrete state space (such as, e.g., data-intensive communication protocols), our technique turns out to be highly effective. Additionally, our framework allows to employ existing highly-optimized implementations for DBMs and BDDs without modifications. Using a prototype implementation, we are able to verify a central correctness property of the physical layer protocol of the FlexRay communication protocol [15] taking an unreliable physical layer into account.