Making the right cut in model checking data-intensive timed systems
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
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In this paper, the authors describe symbolic model checking for real-time systems based on approximation. It is important to determine how to reduce the increase in verification cost due to timed-state processing during symbolic model checking of a real-time system. Verification techniques that use a set of approximate states instead of exact timed states in a reachability analysis of a real-time system have been proposed to increase the effect in reducing the verification cost. Therefore, the authors propose a symbolic model checking technique for real-time systems that uses a set of approximate states. The verification algorithm calculates the set of approximate states by performing fixpoint calculations based on an approximation corresponding to a computation tree logic (CTL) formula. The authors implemented the proposed algorithm and compared it with existing real-time symbolic model checkers. They obtained results showing that the proposed technique is effective for verifying a large-scale system that includes many clock variables. © 2004 Wiley Periodicals, Inc. Syst Comp Jpn, 35(10): 83–101, 2004; Published online in Wiley InterScience (). DOI 10.1002/scj.10565