Computation of minimal counterexamples by using black box techniques and symbolic methods
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
SMT '08/BPR '08 Proceedings of the Joint Workshops of the 6th International Workshop on Satisfiability Modulo Theories and 1st International Workshop on Bit-Precise Reasoning
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
Quantifier Elimination via Functional Composition
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
An AIG-Based QBF-solver using SAT for preprocessing
Proceedings of the 47th Design Automation Conference
Exploiting structure in an AIG based QBF solver
Proceedings of the Conference on Design, Automation and Test in Europe
Making the right cut in model checking data-intensive timed systems
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Fully symbolic model checking for timed automata
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Incremental preprocessing methods for use in BMC
Formal Methods in System Design
Automatic verification of hybrid systems with large discrete state space
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Exact and fully symbolic verification of linear hybrid automata with large discrete state spaces
Science of Computer Programming
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In this paper we present a complete method for verifying properties expressed in the temporal logic CTL. In contrast to the majority of verification methods presented in recent years, we support unbounded model checking based on symbolic representations of characteristic functions. Among others, our method is based on an advanced And-Inverter Graph (AIG) implementation, quantifier scheduling, and BDD sweeping. For several examples, our method outperforms BDD based symbolic model checking by orders of magnitude. However, our approach is also able to produce competitive results for cases where BDD are known to perform well.