Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
On a generalization of extended resolution
Discrete Applied Mathematics - Special issue on the satisfiability problem and Boolean functions
Bounded Model Checking Using Satisfiability Solving
Formal Methods in System Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Accelerating Bounded Model Checking of Safety Properties
Formal Methods in System Design
Advanced Unbounded Model Checking Based on AIGs, BDD Sweeping, And Quantifier Scheduling
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs
MTV '06 Proceedings of the Seventh International Workshop on Microprocessor Test and Verification
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
VMCAI'10 Proceedings of the 11th international conference on Verification, Model Checking, and Abstract Interpretation
Effective preprocessing in SAT through variable and clause elimination
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Efficient SAT solving under assumptions
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
Preprocessing in incremental SAT
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
Incremental QBF preprocessing for partial design verification
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
Small-delay-fault ATPG with waveform accuracy
Proceedings of the International Conference on Computer-Aided Design
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Traditional incremental SAT solvers have achieved great success in the domain of Bounded Model Checking (BMC). Recently, modern solvers have introduced advanced preprocessing procedures that have allowed them to obtain high levels of performance. Unfortunately, many preprocessing techniques such as variable and (blocked) clause elimination cannot be directly used in an incremental manner. This work focuses on extending these techniques and Craig interpolation so that they can be used effectively together in incremental SAT solving (in the context of BMC). The techniques introduced here doubled the performance of our BMC solver on both SAT and UNSAT problems. For UNSAT problems, preprocessing had the added advantage that Craig interpolation was able to find the fixed point sooner, reducing the number of incremental SAT iterations. Furthermore, our ideas seem to perform better as the benchmarks become larger, and/or deeper, which is exactly when they are needed. Lastly, our methods can be integrated into other SAT based BMC tools to achieve similar speedups.