Formal methods: state of the art and future directions
ACM Computing Surveys (CSUR) - Special ACM 50th-anniversary issue: strategic directions in computing research
Tearing based automatic abstraction for CTL model checking
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
CTL model checking based on forward state traversal
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An Industrial Strength Theorem Prover for a Logic Based on Common Lisp
IEEE Transactions on Software Engineering
Formal verification of FIRE: a case study
DAC '97 Proceedings of the 34th annual Design Automation Conference
Toward formalizing a validation methodology using simulation coverage
DAC '97 Proceedings of the 34th annual Design Automation Conference
Reachability analysis using partitioned-ROBDDs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Forward model checking techniques oriented to buggy designs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Improving efficiency of symbolic model checking for state-based system requirements
Proceedings of the 1998 ACM SIGSOFT international symposium on Software testing and analysis
WELD—an environment for Web-based electronic design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Approximation and decomposition of binary decision diagrams
DAC '98 Proceedings of the 35th annual Design Automation Conference
Incremental CTL model checking using BDD subsetting
DAC '98 Proceedings of the 35th annual Design Automation Conference
Hybrid verification using saturated simulation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Hybrid techniques for fast functional simulation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Verification of RTL generated from scheduled behavior in a high-level synthesis flow
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Design of experiments in BDD variable ordering: lessons learned
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The Synchronous Approach to Designing Reactive Systems
Formal Methods in System Design - Special issue: industrial critical systems
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Cache-conscious structure layout
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
Symbolic reachability analysis of large finite state machines using don't cares
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Enhancing simulation with BDDs and ATPG
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Buffer minimization in pass transistor logic
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
Proceedings of the 37th Annual Design Automation Conference
Efficient methods for embedded system design space exploration
Proceedings of the 37th Annual Design Automation Conference
Implicit enumeration of strongly connected components
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Least fixpoint approximations for reachability analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Formal specification and verification of a dataflow processor array
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Synchronous equivalence for embedded systems: a tool for design exploration
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Power and delay reduction via simultaneous logic and placement optimization in FPGAs
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Iterative abstraction-based CTL model checking
DATE '00 Proceedings of the conference on Design, automation and test in Europe
LPSAT: a unified approach to RTL satisfiability
Proceedings of the conference on Design, automation and test in Europe
Model abstraction for formal verification
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Rarity based guided state space search
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
A new partitioning scheme for improvement of image computation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Logic optimization and code generation for embedded control applications
Proceedings of the ninth international symposium on Hardware/software codesign
Partial-Order Reduction in Symbolic State-Space Exploration
Formal Methods in System Design - Special issue on CAV '97
Dynamic detection and removal of inactive clauses in SAT with application in image computation
Proceedings of the 38th annual Design Automation Conference
JMOCHA: a model checking tool that exploits design structure
ICSE '01 Proceedings of the 23rd International Conference on Software Engineering
Modular verification of collaboration-based software designs
Proceedings of the 8th European software engineering conference held jointly with 9th ACM SIGSOFT international symposium on Foundations of software engineering
An error simulation based approach to measure error coverage of formal properties
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Formal verification of module interfaces against real time specifications
Proceedings of the 39th annual Design Automation Conference
Multiple-valued logic synthesis and optimization
Logic Synthesis and Verification
SIVA: A System for Coverage-Directed State Space Search
Journal of Electronic Testing: Theory and Applications
Don't cares and multi-valued logic network minimization
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Partition-based decision heuristics for image computation using SAT and BDDs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Bisimulation Minimization and Symbolic Model Checking
Formal Methods in System Design
Verification of a Radio-Based Signaling System Using the STATEMATE Verification Environment
Formal Methods in System Design
Comparing HOL and MDG: a case study on the verification of an ATM switch fabric
Nordic Journal of Computing
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
Formal Methods in System Design
And/Or Hierarchies and Round Abstraction
MFCS '00 Proceedings of the 25th International Symposium on Mathematical Foundations of Computer Science
Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Techniques for Implicit State Enumeration of EFSMs
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Three Approaches to Hardware Verification: HOL, MDG and VIS Compared
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Bisimulation Minimization in an Automata-Theoretic Verification Framework
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
SAT-Based Image Computation with Application in Reachability Analysis
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Border-Block Triangular Form and Conjunction Schedule in Image Computation
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
B2M: A Semantic Based Tool for BLIF Hardware Descriptions
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Speeding Up Image Computation by Using RTL Information
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Sharp Disjunctive Decomposition for Language Emptiness Checking
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
A Fixpoint Based Encoding for Bounded Model Checking
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Analysis of Symbolic SCC Hull Algorithms
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Model Checking Support for the ASM High-Level Language
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Is There a Best Symbolic Cycle-Detection Algorithm?
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Branching vs. Linear Time: Final Showdown
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
A HOL Conversion for Translating Linear Time Temporal Logic to omega-Automata
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Automating Modular Verification
CONCUR '99 Proceedings of the 10th International Conference on Concurrency Theory
Divide and Compose: SCC Refinement for Language Emptiness
CONCUR '01 Proceedings of the 12th International Conference on Concurrency Theory
Bisimulation and Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Verifying a Time-Triggered Protocol in a Multi-language Environment
SAFECOMP '98 Proceedings of the 17th International Conference on Computer Safety, Reliability and Security
Random 3-SAT: The Plot Thickens
CP '02 Proceedings of the 6th International Conference on Principles and Practice of Constraint Programming
Random 3-SAT and BDDs: The Plot Thickens Further
CP '01 Proceedings of the 7th International Conference on Principles and Practice of Constraint Programming
Coverage Directed Generation of System-Level Test Cases for the Validation of a DSP System
FME '01 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods for Increasing Software Productivity
Efficient Decision Procedures for Model Checking of Linear Time Logic Properties
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
NUSMV: A New Symbolic Model Verifier
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Model Checking Based on Sequential ATPG
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Verifying Network Protocol Implementations by Symbolic Refinement Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Transformation-Based Verification Using Generalized Retiming
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Automatic Abstraction for Verification of Timed Circuits and Systems
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Exploiting Behavioral Hierarchy for Efficient Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Towards a Methodology for Model Checking ASM: Lessons Learned from the FLASH Case Study
ASM '00 Proceedings of the International Workshop on Abstract State Machines, Theory and Applications
Model Checking Object-Z Using ASM
IFM '02 Proceedings of the Third International Conference on Integrated Formal Methods
A comprehensive approach to the partial scan problem using implicit state enumeration
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Fine-Grain Conjunction Scheduling for Symbolic Reachability Analysis
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Language emptiness checking using MDGs
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Automated verification using deduction, exploration, and abstraction
Programming methodology
Dos and don'ts of CTL state coverage estimation
Proceedings of the 40th annual Design Automation Conference
The Quest for Correct Systems: Model Checking of Diagrams and Datatypes
APSEC '99 Proceedings of the Sixth Asia Pacific Software Engineering Conference
Formal Verification of Digital Systems
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Property-Specific Testbench Generation for Guided Simulation
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Open Computation Tree Logic for Formal Verification of Modules
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Improved SAT-based Bounded Reachability Analysis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Feature specification and automated conflict detection
ACM Transactions on Software Engineering and Methodology (TOSEM)
WWW.BDD-Portal.ORG: an experimentation platform for binary decision diagram algorithms
Experimental algorithmics
Algorithms and heuristics in VLSI design
Experimental algorithmics
Reactive and Real-Time Systems Course: How to Get the Most Out of it
Real-Time Systems
Random 3-SAT: The Plot Thickens
Constraints
From Pre-Historic to Post-Modern Symbolic Model Checking
Formal Methods in System Design
MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Safety Property Verification Using Sequential SAT and Bounded Model Checking
IEEE Design & Test
Refining the SAT decision ordering for bounded model checking
Proceedings of the 41st annual Design Automation Conference
SATORI - A Fast Sequential SAT Engine for Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
The Compositional Far Side of Image Computation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On compliance test of on-chip bus for SOC
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Efficient reachability checking using sequential SAT
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Online Cycle Detection and Difference Propagation: Applications to Pointer Analysis
Software Quality Control
Fast Computation of Data Correlation Using BDDs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
From linear time to branching time
ACM Transactions on Computational Logic (TOCL)
Forward image computation with backtracing ATPG and incremental state-set construction
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
FPGA technology mapping: a study of optimality
Proceedings of the 42nd annual Design Automation Conference
Prime clauses for fast enumeration of satisfying assignments to boolean circuits
Proceedings of the 42nd annual Design Automation Conference
Dynamic abstraction using SAT-based BMC
Proceedings of the 42nd annual Design Automation Conference
Application of Wu's method to symbolic model checking
Proceedings of the 2005 international symposium on Symbolic and algebraic computation
Functional test generation based on word-level SAT
Journal of Systems Architecture: the EUROMICRO Journal
Incremental deductive & inductive reasoning for SAT-based bounded model checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient computation of small abstraction refinements
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ACM Transactions on Embedded Computing Systems (TECS)
A comparison of BDDs, BMC, and sequential SAT for model checking
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Compositional SCC Analysis for Language Emptiness
Formal Methods in System Design
Transition-based coverage estimation for symbolic model checking
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Word level functional coverage computation
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A Technique for Estimating the Difficulty of a Formal Verification Problem
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
RTL SAT simplification by Boolean and interval arithmetic reasoning
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Automatic insertion of low power annotations in RTL for pipelined microprocessors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Equivalence verification of arithmetic datapaths with multiple word-length operands
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Optimizing sequential cycles through Shannon decomposition and retiming
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Disjunctive image computation for embedded software verification
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Guiding simulation with increasingly refined abstract traces
Proceedings of the 43rd annual Design Automation Conference
Formal analysis of hardware requirements
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Automatic invariant strengthening to prove properties in bounded model checking
Proceedings of the 43rd annual Design Automation Conference
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs
IEEE Transactions on Computers
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Disjunctive image computation for software verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Bounded Model Checking with Parametric Data Structures
Electronic Notes in Theoretical Computer Science (ENTCS)
An effective guidance strategy for abstraction-guided simulation
Proceedings of the 44th annual Design Automation Conference
Efficient field-sensitive pointer analysis of C
ACM Transactions on Programming Languages and Systems (TOPLAS)
Sequential circuits for program analysis
Proceedings of the twenty-second IEEE/ACM international conference on Automated software engineering
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Computation of minimal counterexamples by using black box techniques and symbolic methods
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Auxiliary state machines + context-triggered properties in verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Improved visibility in one-to-many trace concretization
Proceedings of the conference on Design, automation and test in Europe
Model Checking and Preprocessing
AI*IA '07 Proceedings of the 10th Congress of the Italian Association for Artificial Intelligence on AI*IA 2007: Artificial Intelligence and Human-Oriented Computing
25 Years of Model Checking
Counterexample Guided Spotlight Abstraction Refinement
FORTE '08 Proceedings of the 28th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
Visualizing potential parallelism in sequential programs
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Reveal: A Formal Verification Tool for Verilog Designs
LPAR '08 Proceedings of the 15th International Conference on Logic for Programming, Artificial Intelligence, and Reasoning
From Philosophical to Industrial Logics
ICLA '09 Proceedings of the 3rd Indian Conference on Logic and Its Applications
Dependent latch identification in the reachable state space
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Enhancing bug hunting using high-level symbolic simulation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
WoLFram- A Word Level Framework for Formal Verification
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Symbolic state traversal for WCET analysis
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Constraints in one-to-many concretization for abstraction refinement
Proceedings of the 46th Annual Design Automation Conference
Synthesis and optimization of pipelined packet processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dependent-latch identification in reachable state space
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Incremental Algorithm to Check Satisfiability for Bounded Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
μ-Calculus Model Checking in Maude
Electronic Notes in Theoretical Computer Science (ENTCS)
CTL-Property Transformations Along an Incremental Design Process
Electronic Notes in Theoretical Computer Science (ENTCS)
Model Checking Temporal Aspects of Inconsistent Concurrent Systems Based on Paraconsistent Logic
Electronic Notes in Theoretical Computer Science (ENTCS)
LSC Verification for UML Models with Unbounded Creation and Destruction
Electronic Notes in Theoretical Computer Science (ENTCS)
Electronic Notes in Theoretical Computer Science (ENTCS)
Verifying VHDL designs with multiple clocks in SMV
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Parallel SAT solving in bounded model checking
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Modelling of complex systems given as a mealy machine with linear decision diagrams
ICCS'03 Proceedings of the 2003 international conference on Computational science: PartII
Automatic fault localization for property checking
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
Detecting design flaws in UML state charts for embedded software
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
Bounded reachability checking of asynchronous systems using decision diagrams
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
Fault localization and correction with QBF
SAT'07 Proceedings of the 10th international conference on Theory and applications of satisfiability testing
RAT: a tool for the formal analysis of requirements
CAV'07 Proceedings of the 19th international conference on Computer aided verification
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Proceedings of the 14th international SPIN conference on Model checking software
Large program trace analysis and compression with ZDDs
Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization
Mind the shapes: abstraction refinement via topology invariants
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
On combining 01X-logic and QBF
EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory
A hybrid algorithm for LTL games
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
Pillars of computer science
Analyzing k-step induction to compute invariants for SAT-based property checking
Proceedings of the 47th Design Automation Conference
Technical Section: ftc-Floating precision texture compression
Computers and Graphics
Strengthening properties using abstraction refinement
Proceedings of the Conference on Design, Automation and Test in Europe
Are logic synthesis tools robust?
Proceedings of the 48th Design Automation Conference
Equivalence checking between function block diagrams and C programs using HW-CBMC
SAFECOMP'11 Proceedings of the 30th international conference on Computer safety, reliability, and security
Evaluating LTL satisfiability solvers
ATVA'11 Proceedings of the 9th international conference on Automated technology for verification and analysis
Exploring structural symmetry automatically in symbolic trajectory evaluation
Formal Methods in System Design
Feasibility analysis for robustness quantification by symbolic model checking
Formal Methods in System Design
Incremental preprocessing methods for use in BMC
Formal Methods in System Design
Benchmarking a model checker for algorithmic improvements and tuning for performance
Formal Methods in System Design
A dynamic assertion-based verification platform for validation of UML designs
ACM SIGSOFT Software Engineering Notes
CirCUs: a hybrid satisfiability solver
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Fifty-five solvers in vancouver: the SAT 2004 competition
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Verifying statemate statecharts using CSP and FDR
ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
Journal of Computer and System Sciences
FPGA logic synthesis using quantified boolean satisfiability
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
Preliminary results of a case study: model checking for advanced automotive applications
FM'05 Proceedings of the 2005 international conference on Formal Methods
Verification of an error correcting code by abstract interpretation
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
Efficient conflict analysis for finding all satisfying assignments of a boolean circuit
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Shortest counterexamples for symbolic model checking of LTL with past
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
ABC: an academic industrial-strength verification tool
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Symbolic systems, explicit properties: on hybrid approaches for LTL symbolic model checking
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
TRANSYT: a tool for the verification of asynchronous concurrent systems
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Interleaved invariant checking with dynamic abstraction
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
A fine-grained fullness-guided chaining heuristic for symbolic reachability analysis
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Efficient abstraction refinement in interpolation-based unbounded model checking
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Computing a hierarchical static order for decision diagram-based representation from p/t nets
Transactions on Petri Nets and Other Models of Concurrency V
Exact and fully symbolic verification of linear hybrid automata with large discrete state spaces
Science of Computer Programming
A safety-focused verification using software fault trees
Future Generation Computer Systems
Survey: Linear Temporal Logic Symbolic Model Checking
Computer Science Review
Strength-Based decomposition of the property Büchi automaton for faster model checking
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Automatized high-level evaluation of security properties for RTL hardware designs
Proceedings of the Workshop on Embedded Systems Security
Specification and Verification of Concurrent Programs Through Refinements
Journal of Automated Reasoning
Synthesis of hierarchical systems
Science of Computer Programming
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