Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Property preserving abstractions for the verification of concurrent systems
Formal Methods in System Design - Special issue on computer-aided verification (based on CAV'92 workshop)
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
The B Language and Method: A Guide to Practical Formal Development
The B Language and Method: A Guide to Practical Formal Development
Model Checking and Modular Verification
CONCUR '91 Proceedings of the 2nd International Conference on Concurrency Theory
MOCHA: Modularity in Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
You Assume, We Guarantee: Methodology and Case Studies
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Incremental formal verification for model refining
Proceedings of the Workshop on Model-Driven Engineering, Verification and Validation
Efficient property preservation checking of model refinements
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
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This paper formalizes an incremental approach to design flow-control oriented hardware devices described by Moore machines. The method is based on successive additions of new behaviors to a simple device in order to build a more complex one. The new behaviors added must not override the previous ones. A set of CTL formulae is assigned to each step of the design. The links between the formulae of two consecutive design steps are formalized as a set of formula-transformations F, stating that : a CTL formula f is satisfied on a design at step i, iff F(f) is satisfied on the design extended at step i+1. This result has been applied during the design of bus protocol converters in the context on non-regression analysis. It could also be applied in order to simplify both system and formulae in particular cases.