Edge-valued binary decision diagrams for multi-level hierarchical verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A technique of state space search based on unfolding
Formal Methods in System Design - Special issue on computer-aided verification (based on CAV'92 workshop)
Model checking
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Bounded Model Checking Using Satisfiability Solving
Formal Methods in System Design
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Formal Methods in System Design
Evaluating Deadlock Detection Methods for Concurrent Software
IEEE Transactions on Software Engineering
Using Edge-Valued Decision Diagrams for Symbolic Generation of Shortest Paths
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Traversal Techniques for Concurrent Systems
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Saturation: An Efficient Iteration Strategy for Symbolic State-Space Generation
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
SAT-Solving the Coverability Problem for Petri Nets
Formal Methods in System Design
The saturation algorithm for symbolic state-space exploration
International Journal on Software Tools for Technology Transfer (STTT) - Special section on Tools and Algorithms for the Construction and Analysis of Systems
Logic and stochastic modeling with SMART
Performance Evaluation - Modelling techniques and tools for computer performance evaluation
Bounded model checking of concurrent programs
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
F-SOFT: software verification platform
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Saturation-based symbolic reachability analysis using conjunctive and disjunctive partitioning
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
New metrics for static variable ordering in decision diagrams
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Advanced features in SMART: the stochastic model checking analyzer for reliability and timing
ACM SIGMETRICS Performance Evaluation Review
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Bounded reachability or model checking is widely believed to work poorly when using decision diagrams instead of SAT procedures. Recent research suggests this to be untrue with regards to synchronous systems, particularly digital circuits. This paper shows that the belief is also a myth for asynchronous systems, such as models specified by Petri nets. We propose Bounded Saturation, a new algorithm to compute bounded state spaces using Multi-way Decision Diagrams (MDDs). This is based on the established Saturation algorithm which benefits from a non-standard search strategy that is very different from breadth-first search. To bound Saturation, we employ Edge-Valued MDDs and rework its search strategy. Experimental results show that our algorithm often, but not always, compares favorably against two SAT-based approaches advocated in the literature for deadlock checking in Petri nets.