Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Edge-valued binary decision diagrams for multi-level hierarchical verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Model checking
Algebric Decision Diagrams and Their Applications
Formal Methods in System Design
Formal Verification Using Edge-Valued Binary Decision Diagrams
IEEE Transactions on Computers
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Symbolic Reachability Analysis Based on SAT-Solvers
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Saturation: An Efficient Iteration Strategy for Symbolic State-Space Generation
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Efficient Reachability Set Generation and Storage Using Decision Diagrams
Proceedings of the 20th International Conference on Application and Theory of Petri Nets
BDD-Based Debugging Of Design Using Language Containment and Fair CTL
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Word Level Symbolic Model Checking: A New Approach for Verifying Arithmetic Circuits
Word Level Symbolic Model Checking: A New Approach for Verifying Arithmetic Circuits
Efficient symbolic state-space construction for asynchronous systems
ICATPN'00 Proceedings of the 21st international conference on Application and theory of petri nets
Implicit data structures for logic and stochastic systems analysis
ACM SIGMETRICS Performance Evaluation Review
Logic and stochastic modeling with SMART
Performance Evaluation - Modelling techniques and tools for computer performance evaluation
Saturation for a General Class of Models
IEEE Transactions on Software Engineering
Exploiting interleaving semantics in symbolic state-space generation
Formal Methods in System Design
Hierarchical Set Decision Diagrams and Automatic Saturation
PETRI NETS '08 Proceedings of the 29th international conference on Applications and Theory of Petri Nets
Symbolic Reachability Analysis of Integer Timed Petri Nets
SOFSEM '09 Proceedings of the 35th Conference on Current Trends in Theory and Practice of Computer Science
Building Efficient Model Checkers using Hierarchical Set Decision Diagrams and Automatic Saturation
Fundamenta Informaticae - Petri Nets 2008
Formal Verification of the NASA Runway Safety Monitor
Electronic Notes in Theoretical Computer Science (ENTCS)
Bounded reachability checking of asynchronous systems using decision diagrams
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Data representation and efficient solution: a decision diagram approach
SFM'07 Proceedings of the 7th international conference on Formal methods for performance evaluation
Verification of software via integration of design and implementation
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Symbolic verification and test generation for a network of communicating FSMs
ATVA'11 Proceedings of the 9th international conference on Automated technology for verification and analysis
EPEW'05/WS-FM'05 Proceedings of the 2005 international conference on European Performance Engineering, and Web Services and Formal Methods, international conference on Formal Techniques for Computer Systems and Business Processes
Ten years of saturation: a petri net perspective
Transactions on Petri Nets and Other Models of Concurrency V
Building Efficient Model Checkers using Hierarchical Set Decision Diagrams and Automatic Saturation
Fundamenta Informaticae - Petri Nets 2008
| Hi-index | 0.00 |
We present a new method for the symbolic construction of shortest paths in reachability graphs. Our algorithm relies on a variant of edge-valued decision diagrams that supports efficient fixed-point iterations for the joint computation of both the reachable states and their distance from the initial states. Once the distance function is known, a shortest path from an initial state to a state satisfying a given condition can be easily obtained. Using a few representative examples, we show how our algorithm is vastly superior, in terms of both memory and space, to alternative approaches that compute the same information, such as ordinary or algebraic decision diagrams.