Edge-valued binary decision diagrams for multi-level hierarchical verification

Reducing BDD size by exploiting functional dependencies

DAC '93 Proceedings of the 30th international Design Automation Conference

BDD based decomposition of logic functions with application to FPGA synthesis

DAC '93 Proceedings of the 30th international Design Automation Conference

Symmetry detection and dynamic variable ordering of decision diagrams

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Verification of arithmetic circuits with binary moment diagrams

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Equivalence checking of datapaths based on canonical arithmetic expressions

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Who are the variables in your neighborhood

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Efficient construction of binary moment diagrams for verifying arithmetic circuits

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Binary decision diagrams and beyond: enabling technologies for formal verification

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Combinational logic synthesis for LUT based field programmable gate arrays

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Bit-level analysis of an SRT divider circuit

DAC '96 Proceedings of the 33rd annual Design Automation Conference

FGILP: an integer linear program solver based on function graphs

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Linear sifting of decision diagrams

DAC '97 Proceedings of the 34th annual Design Automation Conference

Word-level decision diagrams, WLCDs and division

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

The Theory of Zero-Suppressed BDDs and the Number of Knight‘s Tours

Formal Methods in System Design

Formal verification of word-level specifications

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Formal verification in hardware design: a survey

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Ordered Binary Decision Diagrams and Minimal Trellises

IEEE Transactions on Computers

Dynamic minimization of word-level decision diagrams

Proceedings of the conference on Design, automation and test in Europe

On WLCDs and the Complexity of Word-Level Decision Diagrams—A Lower Bound for Division

Formal Methods in System Design

Factored Edge-Valued Binary Decision Diagrams

Formal Methods in System Design

The K*BMD: A Verification Data Structure

IEEE Design & Test

Formal Verification Using Edge-Valued Binary Decision Diagrams

IEEE Transactions on Computers

Verifying integrity of decision diagrams

Integration, the VLSI Journal

Minimization of word-level decision diagrams

Integration, the VLSI Journal

Using Edge-Valued Decision Diagrams for Symbolic Generation of Shortest Paths

FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design

Verifying Integrity of Decision Diagrams

SAFECOMP '98 Proceedings of the 17th International Conference on Computer Safety, Reliability and Security

Bisimulation Algorithms for Stochastic Process Algebras and Their BDD-Based Implementation

ARTS '99 Proceedings of the 5th International AMAST Workshop on Formal Methods for Real-Time and Probabilistic Systems

K*BMDs: A New Data Structure for Verification

EDTC '96 Proceedings of the 1996 European conference on Design and Test

Formal Verification of Combinational Circuit

VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Probabilistic decision graphs-combining verification and AI techniques for probabilistic inference

International Journal of Uncertainty, Fuzziness and Knowledge-Based Systems - New trends in probabilistic graphical models

Implicit pseudo boolean enumeration algorithms for input vector control

Proceedings of the 41st annual Design Automation Conference

AND/OR multi-valued decision diagrams (AOMDDs) for graphical models

Journal of Artificial Intelligence Research

Bounded reachability checking of asynchronous systems using decision diagrams

TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems

Data representation and efficient solution: a decision diagram approach

SFM'07 Proceedings of the 7th international conference on Formal methods for performance evaluation

Symbolic partition refinement with automatic balancing of time and space

Performance Evaluation

Interactive cost configuration over decision diagrams

Journal of Artificial Intelligence Research

Logic design error diagnosis and correction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Semiring labelled decision diagrams, revisited: canonicity and spatial efficiency issues

IJCAI'13 Proceedings of the Twenty-Third international joint conference on Artificial Intelligence