Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Formal Verification of Digital Circuits Using Symbolic Ternary System Models
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Verifying Temporal Properties of Sequential Machines Without Building their State Diagrams
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Model checking and abstraction
POPL '92 Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Validating discrete event simulations using event pattern mappings
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Edge-valued binary decision diagrams for multi-level hierarchical verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Inductive verification of iterative systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Comparative design validation based on event pattern mappings
DAC '93 Proceedings of the 30th international Design Automation Conference
Minimum length synchronizing sequences of finite state machine
DAC '93 Proceedings of the 30th international Design Automation Conference
Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
CTL model checking based on forward state traversal
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Using complete-1-distinguishability for FSM equivalence checking
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Reachability analysis using partitioned-ROBDDs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Approximation and decomposition of binary decision diagrams
DAC '98 Proceedings of the 35th annual Design Automation Conference
The General Product Machine: a New Model for Symbolic FSM Traversal
Formal Methods in System Design
Automatic compositional minimization in CTL model checking
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Symbolic reachability analysis of large finite state machines using don't cares
DATE '99 Proceedings of the conference on Design, automation and test in Europe
To split or to conjoin: the question in image computation
Proceedings of the 37th Annual Design Automation Conference
Lazy group sifting for efficient symbolic state traversal of FSMs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Application of linearly transformed BDDs in sequential verification
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A 3-step approach for performance-driven whole-chip routing
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Partial-Order Reduction in Symbolic State-Space Exploration
Formal Methods in System Design - Special issue on CAV '97
Using complete-1-distinguishability for FSM equivalence checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Bounded Model Checking Using Satisfiability Solving
Formal Methods in System Design
Non-linear quantification scheduling in image computation
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Algebric Decision Diagrams and Their Applications
Formal Methods in System Design
L.0: A Truly Concurrent Executable Temporal Logic Language for Protocols
IEEE Transactions on Software Engineering
Using Combinatorial Optimization Methods for Quantification Scheduling
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Efficient Decision Procedures for Model Checking of Linear Time Logic Properties
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
NUSMV: A New Symbolic Model Verifier
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Information and Computation - Special issue: LICS'97
Handbook of automated reasoning
An approach to hierarchy model checking via evaluating CTL hierarchically
ATS '95 Proceedings of the 4th Asian Test Symposium
Efficient Preimage Computation Using A Novel Success-Driven ATPG
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Reduced Test Application Time Based on Reachability Analysis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Transition-by-transition FSM traversal for reachability analysis in bounded model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Disjunctive image computation for embedded software verification
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Fast falsification based on symbolic bounded property checking
Proceedings of the 43rd annual Design Automation Conference
Disjunctive image computation for software verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Decomposing image computation for symbolic reachability analysis using control flow information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Automated Rule-Based Diagnosis through a Distributed Monitor System
IEEE Transactions on Dependable and Secure Computing
Auxiliary state machines + context-triggered properties in verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Model checking sequential software programs via mixed symbolic analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Enhancing bug hunting using high-level symbolic simulation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Static Analysis of Concurrent Programs Using Ordinary Differential Equations
ICTAC '09 Proceedings of the 6th International Colloquium on Theoretical Aspects of Computing
An Improvement of Software Architecture Verification
Electronic Notes in Theoretical Computer Science (ENTCS)
Distributed Symbolic Bounded Property Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Hypergraph partitioning for the parallel computation of continuous Petri nets
PaCT'11 Proceedings of the 11th international conference on Parallel computing technologies
CirCUs: a hybrid satisfiability solver
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Checking system boundedness using ordinary differential equations
Information Sciences: an International Journal
Parallel computation of continuous Petri nets based on hypergraph partitioning
The Journal of Supercomputing
Hypergraph partitioning for the parallel computing of fuzzy differential equations
Fuzzy Sets and Systems
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