Distributed Symbolic Bounded Property Checking

Authors:
Pradeep K. Nalla;Roland J. Weiss;Prakash Peranandam;Jürgen Ruf;Thomas Kropf;Wolfgang Rosenstiel
Affiliations:
Wilhelm-Schickard-Institut für Informatik, Universität Tübingen, Sand 13, 72076 Tübingen, Germany;Wilhelm-Schickard-Institut für Informatik, Universität Tübingen, Sand 13, 72076 Tübingen, Germany;Wilhelm-Schickard-Institut für Informatik, Universität Tübingen, Sand 13, 72076 Tübingen, Germany;Wilhelm-Schickard-Institut für Informatik, Universität Tübingen, Sand 13, 72076 Tübingen, Germany;Wilhelm-Schickard-Institut für Informatik, Universität Tübingen, Sand 13, 72076 Tübingen, Germany;Wilhelm-Schickard-Institut für Informatik, Universität Tübingen, Sand 13, 72076 Tübingen, Germany
Venue:
Electronic Notes in Theoretical Computer Science (ENTCS)
Year:
2006

Citing 16
Cited 1

Representing circuits more efficiently in symbolic model checking

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams

ACM Computing Surveys (CSUR)
Symbolic model checking: 1020 states and beyond

Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
High-density reachability analysis

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Improved reachability analysis of large finite state machines

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Partitioned ROBDDs—a compact, canonical and efficiently manipulable representation for Boolean functions

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Disjunctive partitioning and partial iterative squaring: an effective approach for symbolic traversal of large circuits

DAC '97 Proceedings of the 34th annual Design Automation Conference
Approximation and decomposition of binary decision diagrams

DAC '98 Proceedings of the 35th annual Design Automation Conference
Model checking

Model checking
Simulation-guided property checking based on a multi-valued AR-automata

Proceedings of the conference on Design, automation and test in Europe
Achieving Scalability in Parallel Reachability Analysis of Very Large Circuits

CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
A Conjunctively Decomposed Boolean Representation for Symbolic Model Checking

CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Parallelizing the Murphi Verifier

CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
On the Efficient Sequential and Distributed Generation of Very Large Markov Chains from Stochastic Petri Nets

PNPM '99 Proceedings of the The 8th International Workshop on Petri Nets and Performance Models
Issues in distributed timed model checking: Building Zeus

International Journal on Software Tools for Technology Transfer (STTT) - Special section on parallel and distributed model checking
Dynamic guiding of bounded property checking

HLDVT '04 Proceedings of the High-Level Design Validation and Test Workshop, 2004. Ninth IEEE International

Distributed BDD-based BMC for the verification of multi-agent systems

Proceedings of the 9th International Conference on Autonomous Agents and Multiagent Systems: volume 1 - Volume 1

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper we describe an algorithm for distributed, BDD-based bounded property checking and its implementation in the verification tool SymC. The distributed algorithm verifies larger models and returns results faster than the sequential version. The core algorithm distributes partitions of the state set to computation nodes after reaching a threshold size. The nodes proceed with image computation on the nodes asynchronously. The main scalability problem of this scheme is the overlap of state set partitions. We present static and dynamic overlap reduction techniques.