Representing circuits more efficiently in symbolic model checking
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-density reachability analysis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Improved reachability analysis of large finite state machines
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Early Quantification and Partitioned Transition Relations
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Verification and Synthesis of Counters Based on Symbolic Techniques
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Reachability analysis using partitioned-ROBDDs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Improving efficiency of symbolic model checking for state-based system requirements
Proceedings of the 1998 ACM SIGSOFT international symposium on Software testing and analysis
Approximation and decomposition of binary decision diagrams
DAC '98 Proceedings of the 35th annual Design Automation Conference
Symbolic reachability analysis of large finite state machines using don't cares
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Improving symbolic traversals by means of activity profiles
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
To split or to conjoin: the question in image computation
Proceedings of the 37th Annual Design Automation Conference
Symbolic guided search for CTL model checking
Proceedings of the 37th Annual Design Automation Conference
Distance driven finite state machine traversal
Proceedings of the 37th Annual Design Automation Conference
A BDD-based satisfiability infrastructure using the unate recursive paradigm
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Sequential equivalence checking without state space traversal
Proceedings of the conference on Design, automation and test in Europe
Application of linearly transformed BDDs in sequential verification
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A 3-step approach for performance-driven whole-chip routing
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Optimizing Symbolic Model Checking for Statecharts
IEEE Transactions on Software Engineering - Special issue on 1999 international conference on software engineering
Efficient state representation for symbolic simulation
Proceedings of the 39th annual Design Automation Conference
Input Elimination and Abstraction in Model Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Techniques for Smaller Intermediary BDDs
CONCUR '01 Proceedings of the 12th International Conference on Concurrency Theory
Hints to accelerate Symbolic Traversal
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Proceedings of the 42nd annual Design Automation Conference
STACCATO: disjoint support decompositions from BDDs through symbolic kernels
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Transition-by-transition FSM traversal for reachability analysis in bounded model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Disjunctive image computation for embedded software verification
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Fast falsification based on symbolic bounded property checking
Proceedings of the 43rd annual Design Automation Conference
Disjunctive image computation for software verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Decomposing image computation for symbolic reachability analysis using control flow information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
GSTE is partitioned model checking
Formal Methods in System Design
Model checking sequential software programs via mixed symbolic analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Exploiting Target Enlargement and Dynamic Abstraction within Mixed BDD and SAT Invariant Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Distributed Symbolic Bounded Property Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
A new reachability algorithm for symmetric multi-processor architecture
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Computing argumentation in polynomial number of BDD operations: a preliminary report
ArgMAS'10 Proceedings of the 7th international conference on Argumentation in Multi-Agent Systems
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Extending the applicability of reachability analysis to large andreal circuits is a key issue.In fact they are still limited forthe following reasons: peak BDD size during image computation,BDD explosion for representing state sets and very highsequential depth.Following the promising trend of partitioning and problem decomposition,we present a new approach based on a disjunctivepartitioned transition relation and on an improved iterativesquaring.In this approach a Finite State Machine is decomposedand traversed one "functioning-mode" at a time bymeans of the "disjunctive" partitioned approach.The overall algorithm aims at lowering the intermediate peakBDD size pushing further reachability analysis.Experimentson a few industrial circuits containing counters and on somelarge benchmarks show the feasibility of the approach.