A BDD-based satisfiability infrastructure using the unate recursive paradigm

Authors:
Priyank Kalla;Zhihong Zeng;Maciej J. Ciesielski;Chilai Huang
Affiliations:
Department of Electrical and Computer Engineering, University of Massachusetts at Amherst, Amherst, MA;Department of Electrical and Computer Engineering, University of Massachusetts at Amherst, Amherst, MA;Department of Electrical and Computer Engineering, University of Massachusetts at Amherst, Amherst, MA;Avery Design Systems, Inc., 2 Atwood Lane, Andover, MA
Venue:
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Year:
2000

Citing 18
Cited 5

Graph-Based Algorithms for Boolean Function Manipulation

IEEE Transactions on Computers
Some results and experiments in programming techniques for propositional logic

Computers and Operations Research - Special issue: Applications of integer programming
Efficient generation of test patterns using Boolean satisfiability

Efficient generation of test patterns using Boolean satisfiability
Efficient implementation of a BDD package

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Reducing BDD size by exploiting functional dependencies

DAC '93 Proceedings of the 30th international Design Automation Conference
New techniques for efficient verification with implicitly conjoined BDDs

DAC '94 Proceedings of the 31st annual Design Automation Conference
Improvements to propositional satisfiability search algorithms

Improvements to propositional satisfiability search algorithms
GRASP—a new search algorithm for satisfiability

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Partitioned ROBDDs—a compact, canonical and efficiently manipulable representation for Boolean functions

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Disjunctive partitioning and partial iterative squaring: an effective approach for symbolic traversal of large circuits

DAC '97 Proceedings of the 34th annual Design Automation Conference
Functional vector generation for HDL models using linear programming and 3-satisfiability

DAC '98 Proceedings of the 35th annual Design Automation Conference
Algorithms for solving Boolean satisfiability in combinational circuits

DATE '99 Proceedings of the conference on Design, automation and test in Europe
A Computing Procedure for Quantification Theory

Journal of the ACM (JACM)
Logic Synthesis and Verification Algorithms

Logic Synthesis and Verification Algorithms
Logic Minimization Algorithms for VLSI Synthesis

Logic Minimization Algorithms for VLSI Synthesis
Computers and Intractability: A Guide to the Theory of NP-Completeness

Computers and Intractability: A Guide to the Theory of NP-Completeness
Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams

ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Explicit and implicit algorithms for binate covering problems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

LPSAT: a unified approach to RTL satisfiability

Proceedings of the conference on Design, automation and test in Europe
Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW

Proceedings of the 38th annual Design Automation Conference
Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors

Journal of Symbolic Computation
Functional test generation based on word-level SAT

Journal of Systems Architecture: the EUROMICRO Journal
Integrating CNF and BDD based SAT solvers

HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop

Quantified Score

Hi-index	0.00

A BDD-based satisfiability infrastructure using the unate recursive paradigm

Quantified Score

Visualization

Abstract