Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Random generation of test instances for logic optimizers
DAC '94 Proceedings of the 31st annual Design Automation Conference
Improvements to propositional satisfiability search algorithms
Improvements to propositional satisfiability search algorithms
Experimental results on the crossover point in random 3-SAT
Artificial Intelligence - Special volume on frontiers in problem solving: phase transitions and complexity
Binary decision diagrams and applications for VLSI CAD
Binary decision diagrams and applications for VLSI CAD
Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
High-level design verification of microprocessors via error modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
Communications of the ACM
Proceedings of the 37th Annual Design Automation Conference
A BDD-based satisfiability infrastructure using the unate recursive paradigm
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A machine program for theorem-proving
Communications of the ACM
ACM Transactions on Computational Logic (TOCL)
Proceedings of the 38th annual Design Automation Conference
Validating the intel pentium 4 microprocessor
Proceedings of the 38th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Bounded Model Checking Using Satisfiability Solving
Formal Methods in System Design
SAT with partial clauses and back-leaps
Proceedings of the 39th annual Design Automation Conference
Boolean satisfiability with transitivity constraints
ACM Transactions on Computational Logic (TOCL)
Heavy-Tailed Phenomena in Satisfiability and Constraint Satisfaction Problems
Journal of Automated Reasoning
The Propositional Formula Checker HeerHugo
Journal of Automated Reasoning
A Discrete Lagrangian-Based Global-SearchMethod for Solving Satisfiability Problems
Journal of Global Optimization
Efficient conflict driven learning in a boolean satisfiability solver
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Faster SAT and smaller BDDs via common function structure
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
New Techniques for Deterministic Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
Collection and Analysis of Microprocessor Design Errors
IEEE Design & Test
Itanium Processor Microarchitecture
IEEE Micro
Towards Provably Complete Stochastic Search Algorithms for Satisfiability
EPIA '01 Proceedings of the10th Portuguese Conference on Artificial Intelligence on Progress in Artificial Intelligence, Knowledge Extraction, Multi-agent Systems, Logic Programming and Constraint Solving
Random Generation of Satisfiable and Unsatisfiable CNF Predicates
Proceedings of the IFIP 12th World Computer Congress on Algorithms, Software, Architecture - Information Processing '92, Volume 1 - Volume I
Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Improvements to the Evaluation of Quantified Boolean Formulae
IJCAI '99 Proceedings of the Sixteenth International Joint Conference on Artificial Intelligence
SAT-Encodings, Search Space Structure, and Local Search Performance
IJCAI '99 Proceedings of the Sixteenth International Joint Conference on Artificial Intelligence
Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Solving Boolean Satisfiability Using Local Search Guided by Unit Clause Elimination
CP '01 Proceedings of the 7th International Conference on Principles and Practice of Constraint Programming
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Formal Verification of VLIW Microprocessors with Speculative Execution
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
Integrating Equivalency Reasoning into Davis-Putnam Procedure
Proceedings of the Seventeenth National Conference on Artificial Intelligence and Twelfth Conference on Innovative Applications of Artificial Intelligence
Using Cutwidth to Improve Symbolic Simulation and Boolean Satisfiability
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Incorporating Timing Constraints in the Efficient Memory Model for Symbolic Ternary Simulation
ICCD '98 Proceedings of the International Conference on Computer Design
Solving Hard Satisfiability Problems: A Unified Algorithm Based on Discrete Lagrange Multipliers
ICTAI '99 Proceedings of the 11th IEEE International Conference on Tools with Artificial Intelligence
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Multi-resolution on compressed sets of clauses
ICTAI '00 Proceedings of the 12th IEEE International Conference on Tools with Artificial Intelligence
A satisfiability procedure for quantified boolean formulae
Discrete Applied Mathematics - The renesse issue on satisfiability
Heuristics based on unit propagation for satisfiability problems
IJCAI'97 Proceedings of the 15th international joint conference on Artifical intelligence - Volume 1
A simplifier for propositional formulas with many binary clauses
IJCAI'01 Proceedings of the 17th international joint conference on Artificial intelligence - Volume 1
Using CSP look-back techniques to solve real-world SAT instances
AAAI'97/IAAI'97 Proceedings of the fourteenth national conference on artificial intelligence and ninth conference on Innovative applications of artificial intelligence
Solving satisfiability in combinational circuits with backtrack search and recursive learning
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Efficient formal verification of pipelined processors with instruction queues
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Using positive equality to prove liveness for pipelined microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Comparison of schemes for encoding unobservability in translation to SAT
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A SAT-based procedure for verifying finite state machines in ACL2
ACL2 '06 Proceedings of the sixth international workshop on the ACL2 theorem prover and its applications
A Quantifier-free First-order Knowledge Logic of Authentication
Fundamenta Informaticae - SPECIAL ISSUE ON CONCURRENCY SPECIFICATION AND PROGRAMMING (CS&P 2005) Ruciane-Nide, Poland, 28-30 September 2005
Visualizing SAT Instances and Runs of the DPLL Algorithm
Journal of Automated Reasoning
Programming with Proofs: Language-Based Approaches to Totally Correct Software
Verified Software: Theories, Tools, Experiments
SAT-based versus CSP-based constraint weighting for satisfiability
AAAI'05 Proceedings of the 20th national conference on Artificial intelligence - Volume 1
Massively parallel evolution of SAT heuristics
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
Validated Proof-Producing Decision Procedures
Electronic Notes in Theoretical Computer Science (ENTCS)
Solving difficult SAT instances using greedy clique decomposition
SARA'07 Proceedings of the 7th International conference on Abstraction, reformulation, and approximation
Compressing propositional proofs by common subproof extraction
EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory
Scalable formula decomposition for propositional satisfiability
Proceedings of the Third C* Conference on Computer Science and Software Engineering
A method for debugging of pipelined processors in formal verification by correspondence checking
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessors
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Automatic formal verification of reconfigurable DSPs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
NuMDG: a new tool for multiway decision graphs construction
Journal of Computer Science and Technology - Special issue on natural language processing
Empirical study of the anatomy of modern sat solvers
SAT'11 Proceedings of the 14th international conference on Theory and application of satisfiability testing
ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering
Extended resolution proofs for conjoining BDDs
CSR'06 Proceedings of the First international computer science conference on Theory and Applications
A new approach to model counting
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
Automatic formal verification of multithreaded pipelined microprocessors
Proceedings of the International Conference on Computer-Aided Design
SMT-COMP: satisfiability modulo theories competition
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Automatic formal verification of liveness for pipelined processors with multicycle functional units
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Extended resolution proofs for symbolic SAT solving with quantification
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
Solving difficult SAT problems by using OBDDs and greedy clique decomposition
FAW-AAIM'12 Proceedings of the 6th international Frontiers in Algorithmics, and Proceedings of the 8th international conference on Algorithmic Aspects in Information and Management
The Multivariate Algorithmic Revolution and Beyond
Formal Analysis of SystemC Designs in Process Algebra
Fundamenta Informaticae
A Quantifier-free First-order Knowledge Logic of Authentication
Fundamenta Informaticae - SPECIAL ISSUE ON CONCURRENCY SPECIFICATION AND PROGRAMMING (CS&P 2005) Ruciane-Nide, Poland, 28-30 September 2005
Improving glucose for incremental SAT solving with assumptions: application to MUS extraction
SAT'13 Proceedings of the 16th international conference on Theory and Applications of Satisfiability Testing
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We compare SAT-checkers and decision diagrams on the evaluation of Boolean formulae produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors. The microprocessors are described in a high-level hardware description language, based on the logic of equality with uninterpreted functions and memories (EUFM). The formal verification is done with Burch and Dill's correctness criterion, using flushing to map the state of the implementation processor to the state of the specification. The EUFM correctness formula is translated to an equivalent Boolean formula by exploiting the property of positive equality, and using the automatic tool EVC. We identify the SAT-checkers Chaff and BerkMin as significantly outperforming the rest of the SAT tools when evaluating the Boolean correctness formulae. We examine ways to enhance the performance of Chaff and BerkMin by variations when generating the Boolean formulae. We reassess optimizations we developed earlier to speed up the formal verification.