Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
MIPS RISC architectures
Efficient validity checking for processor verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Practical Decision Procedure for Arithmetic with Function Symbols
Journal of the ACM (JACM)
Fast Decision Procedures Based on Congruence Closure
Journal of the ACM (JACM)
Proceedings of the 37th Annual Design Automation Conference
Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Herbrand Automata for Hardware Verification
CONCUR '98 Proceedings of the 9th International Conference on Concurrency Theory
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Formal Verification of VLIW Microprocessors with Speculative Execution
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Boolean Satisfiability with Transitivity Constraints
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Proceedings of the 38th annual Design Automation Conference
Boolean satisfiability with transitivity constraints
ACM Transactions on Computational Logic (TOCL)
The small model property: how small can it be?
Information and Computation
Modeling and Verification of Out-of-Order Microprocessors in UCLID
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
On Solving Presburger and Linear Arithmetic with SAT
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Deciding Separation Formulas with SAT
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Journal of Symbolic Computation
A hybrid SAT-based decision procedure for separation logic with uninterpreted functions
Proceedings of the 40th annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Efficient formal verification of pipelined processors with instruction queues
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Automatic abstraction and verification of verilog models
Proceedings of the 41st annual Design Automation Conference
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Using positive equality to prove liveness for pipelined microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Refinement strategies for verification methods based on datapath abstraction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Formal Verification of Pipelined Microprocessors with Delayed Branches
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Building small equality graphs for deciding equality logic with uninterpreted functions
Information and Computation
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs
IEEE Transactions on Computers
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Distributing the Workload in a Lazy Theorem-Prover
Electronic Notes in Theoretical Computer Science (ENTCS)
A New Approach for the Construction of Multiway Decision Graphs
Proceedings of the 5th international colloquium on Theoretical Aspects of Computing
Differential symbolic execution
Proceedings of the 16th ACM SIGSOFT International Symposium on Foundations of software engineering
New results on rewrite-based satisfiability procedures
ACM Transactions on Computational Logic (TOCL)
Integrated verification approach during ADL-driven processor design
Microelectronics Journal
A Term Rewriting Technique for Decision Graphs
Electronic Notes in Theoretical Computer Science (ENTCS)
Theory decision by decomposition
Journal of Symbolic Computation
Reduced Functional Consistency of Uninterpreted Functions
Electronic Notes in Theoretical Computer Science (ENTCS)
Building small equality graphs for deciding equality logic with uninterpreted functions
Information and Computation
A method for debugging of pipelined processors in formal verification by correspondence checking
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessors
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Automatic formal verification of reconfigurable DSPs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
NuMDG: a new tool for multiway decision graphs construction
Journal of Computer Science and Technology - Special issue on natural language processing
Automated formal verification of processors based on architectural models
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering
Decision procedures for SAT, SAT modulo theories and beyond. the barcelogictools
LPAR'05 Proceedings of the 12th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
MDG-SAT: an automated methodology for efficient safety checking
International Journal of Critical Computer-Based Systems
Automatic formal verification of multithreaded pipelined microprocessors
Proceedings of the International Conference on Computer-Aided Design
Yet another decision procedure for equality logic
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Decision procedures customized for formal verification
CADE' 20 Proceedings of the 20th international conference on Automated Deduction
Automatic formal verification of liveness for pipelined processors with multicycle functional units
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Producing and verifying extremely large propositional refutations
Annals of Mathematics and Artificial Intelligence
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The logic of Equality with Uninterpreted Functions (EUF) provides a means of abstracting the manipulation of data by a processor when verifying the correctness of its control logic. By reducing formulas in this logic to propositional formulas, we can apply Boolean methods such as ordered Binary Decision Diagrams (BDDs) and Boolean satisfiability checkers to perform the verification. We can exploit characteristics of the formulas describing the verification conditions to greatly simplfy the propostional formulas generated. We identify a class of terms we call “p-terms” for which equality comparisons can only be used in monotonically positive formulas. By applying suitable abstractions to the hardware model, we can express the functionality of data values and instruction addresses flowing through an instruction pipeline with p-terms. A decision procedure can exploit the restricted uses of p-terms by considering only “maximally diverse” interpretations of the associated function symbols, where every function application yields a different value execept when constrainted by functional consistency. We present two methods to translate formulas in EUF into propositional logic. The first interprets the formula over a domain of fixed-length bit vectors and uses vectors of propositional variables to encode domain variables. The second generates formulas encoding the conditions under which pairs of terms have equal valuations, introducing propostional variables to encode the equality relations between pairs of terms. Both of these approaches can exploit maximal diversity to greatly reduce the number of propositional variables that need to be introduced and to reduce the overall formula sizes. We present experimental results demonstrating the efficiency of this approach when verifying pipelined processors using the method proposed by Burch and Dill. Exploiting positive equality allows us to overcome the experimental blow-up experienced previously when verifying microprocessors with load, store, and branch instructions.