Exploiting positive equality and partial non-consistency in the formal verification of pipelined microprocessors

Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic

ACM Transactions on Computational Logic (TOCL)

BDD Based Procedures for a Theory of Equality with Uninterpreted Functions

Formal Methods in System Design

Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors

TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems

Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic

CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods

Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors

Proceedings of the conference on Design, automation and test in Europe - Volume 1

Efficient formal verification of pipelined processors with instruction queues

Proceedings of the 14th ACM Great Lakes symposium on VLSI

Efficient translation of boolean formulas to CNF in formal verification of microprocessors

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Using positive equality to prove liveness for pipelined microprocessors

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

Formal Verification of Pipelined Microprocessors with Delayed Branches

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

A method for debugging of pipelined processors in formal verification by correspondence checking

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessors

ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering

Automatic formal verification of reconfigurable DSPs

Proceedings of the 16th Asia and South Pacific Design Automation Conference

Exploiting abstraction for efficient formal verification of DSPs with arrays of reconfigurable functional units

ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering

Automatic formal verification of multithreaded pipelined microprocessors

Proceedings of the International Conference on Computer-Aided Design

Automatic formal verification of liveness for pipelined processors with multicycle functional units

CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods

From propositional satisfiability to satisfiability modulo theories

SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing

Building efficient decision procedures on top of SAT solvers

SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems