Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
ACM Transactions on Computational Logic (TOCL)
Teaching future verification engineers: the forgotten side of logic design
Proceedings of the 38th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Boolean satisfiability with transitivity constraints
ACM Transactions on Computational Logic (TOCL)
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
The small model property: how small can it be?
Information and Computation
Collection and Analysis of Microprocessor Design Errors
IEEE Design & Test
Itanium Processor Microarchitecture
IEEE Micro
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Relating Multi-step and Single-Step Microprocessor Correctness Statements
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Formal Verification of VLIW Microprocessors with Speculative Execution
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Journal of Symbolic Computation
Experience with Term Level Modeling and Verification of the M*Core microprocessor Core.
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Using positive equality to prove liveness for pipelined microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Functional Verification of Programmable Embedded Architectures: A Top-Down Approach
Functional Verification of Programmable Embedded Architectures: A Top-Down Approach
A new clause learning scheme for efficient unsatisfiability proofs
AAAI'08 Proceedings of the 23rd national conference on Artificial intelligence - Volume 3
A lightweight component caching scheme for satisfiability solvers
SAT'07 Proceedings of the 10th international conference on Theory and applications of satisfiability testing
Automatic formal verification of liveness for pipelined processors with multicycle functional units
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Integrating formal verification into an advanced computer architecture course
IEEE Transactions on Education
Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessors
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Automatic formal verification of reconfigurable DSPs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering
Automatic formal verification of multithreaded pipelined microprocessors
Proceedings of the International Conference on Computer-Aided Design
Formal Verification and Debugging of Precise Interrupts on High Performance Microprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Presented is a method for debugging of pipelined processors in their formal verification with the highly automatic and scalable approach of Correspondence Checking, where a pipelined/superscalar/VLIW implementation is compared against a non-pipelined specification via an inductive correctness criterion based on symbolic simulation in a way that guarantees the correctness of the implementation for all possible execution scenarios. The benefit from the proposed method increases with the complexity of the processor under formal verification. For a 12-stage VLIW processor that imitates the Intel Itanium in many features, the method reduced the size of the EUFM correctness formulas from buggy processors by up to an order of magnitude, the number of Boolean variables in the equivalent propositional correctness formulas and the number of 1s in the counterexample traces by up to 2 orders of magnitude, and resulted in an average speedup in detecting the bugs of 2 orders of magnitude, thus increasing the productivity of the processor designers.