Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
ACM Transactions on Computational Logic (TOCL)
Translation Validation for Synchronous Languages
ICALP '98 Proceedings of the 25th International Colloquium on Automata, Languages and Programming
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Boolean Satisfiability with Transitivity Constraints
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
On Shostak's Decision Procedure for Combinations of Theories
CADE-13 Proceedings of the 13th International Conference on Automated Deduction: Automated Deduction
Compiler verification: a bibliography
ACM SIGSOFT Software Engineering Notes
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Efficient formal verification of pipelined processors with instruction queues
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Using positive equality to prove liveness for pipelined microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Building small equality graphs for deciding equality logic with uninterpreted functions
Information and Computation
Predicate learning and selective theory deduction for a difference logic solver
Proceedings of the 43rd annual Design Automation Conference
Generating Minimum Transitivity Constraints in P-time for Deciding Equality Logic
Electronic Notes in Theoretical Computer Science (ENTCS)
Regression Verification - A Practical Way to Verify Programs
Verified Software: Theories, Tools, Experiments
EufDpll - A Tool to Check Satisfiability of Equality Logic Formulas
Electronic Notes in Theoretical Computer Science (ENTCS)
Word level bitwidth reduction for unbounded hardware model checking
Formal Methods in System Design
Reduced Functional Consistency of Uninterpreted Functions
Electronic Notes in Theoretical Computer Science (ENTCS)
Building small equality graphs for deciding equality logic with uninterpreted functions
Information and Computation
A method for debugging of pipelined processors in formal verification by correspondence checking
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessors
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Automatic formal verification of reconfigurable DSPs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering
Monotonicity Inference for Higher-Order Formulas
Journal of Automated Reasoning
Deciding separation logic formulae by SAT and incremental negative cycle elimination
LPAR'05 Proceedings of the 12th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Automatic formal verification of multithreaded pipelined microprocessors
Proceedings of the International Conference on Computer-Aided Design
A BDD-Representation for the logic of equality and uninterpreted functions
MFCS'05 Proceedings of the 30th international conference on Mathematical Foundations of Computer Science
Yet another decision procedure for equality logic
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Automatic formal verification of liveness for pipelined processors with multicycle functional units
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Monotonicity inference for higher-order formulas
IJCAR'10 Proceedings of the 5th international conference on Automated Reasoning
SDSAT: tight integration of small domain encoding and lazy approaches in a separation logic solver
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
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Efficient decision procedures for equality logic (quantifier-free predicate calculus + the equality sign) are of major importance when proving logical equivalence between systems. We introduce an efficient decision procedure for the theory of equality based on finite instantiations. The main idea is to analyze the structure of the formula and compute accordingly a small domain to each variable such that the formula is satisfiable iff it can be satisfied over these domains. We show how the problem of finding these small domains can be reduced to an interesting graph theoretic problem. This method enabled us to verify formulas containing hundreds of integer and floating point variables that could not be efficiently handled with previously known techniques.