Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
ACM Transactions on Computational Logic (TOCL)
Proceedings of the 38th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Validity Checking for Combinations of Theories with Equality
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
The Power of QDDs (Extended Abstract)
SAS '97 Proceedings of the 4th International Symposium on Static Analysis
Symbolic Model Checking with Rich ssertional Languages
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
On-the-Fly Analysis of Systems with Unbounded, Lossy FIFO Channels
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Deciding Equality Formulas by Small Domains Instantiations
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Boolean Satisfiability with Transitivity Constraints
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Microarchitecture Verification by Compositional Model Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Deciding Separation Formulas with SAT
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Symbolic Model Checking of Infinite State Systems Using Presburger Arithmetic
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PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
The small model property: how small can it be?
Information and Computation
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Deciding Separation Formulas with SAT
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
A hybrid SAT-based decision procedure for separation logic with uninterpreted functions
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Proceedings of the conference on Design, automation and test in Europe - Volume 1
Automatic abstraction and verification of verilog models
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Verification of Embedded Memory Systems using Efficient Memory Modeling
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Refinement Maps for Efficient Verification of Processor Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Automatic discovery of API-level exploits
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Word level predicate abstraction and refinement for verifying RTL verilog
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Science of Computer Programming
Verifying properties of well-founded linked lists
Conference record of the 33rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
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Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Verification of executable pipelined machines with bit-level interfaces
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A complete compositional reasoning framework for the efficient verification of pipelined machines
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Monolithic verification of deep pipelines with collapsed flushing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Parameterised boolean equation systems
Theoretical Computer Science - Formal methods for components and objects
Building small equality graphs for deciding equality logic with uninterpreted functions
Information and Computation
Predicate learning and selective theory deduction for a difference logic solver
Proceedings of the 43rd annual Design Automation Conference
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs
IEEE Transactions on Computers
Propositional Satisfiability and Constraint Programming: A comparative survey
ACM Computing Surveys (CSUR)
EXE: automatically generating inputs of death
Proceedings of the 13th ACM conference on Computer and communications security
Embedded software verification using symbolic execution and uninterpreted functions
International Journal of Parallel Programming
Fast congruence closure and extensions
Information and Computation
Automatic memory reductions for RTL model verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Accelerating high-level bounded model checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Improvements to combinational equivalence checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
SMT(CLU): a step toward scalability in system verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Combining Theorem Proving with Model Checking through Predicate Abstraction
IEEE Design & Test
EHSAT: an efficient RTL satisfiability solver using an extended DPLL procedure
Proceedings of the 44th annual Design Automation Conference
Predicate abstraction with indexed predicates
ACM Transactions on Computational Logic (TOCL)
Formal verification at higher levels of abstraction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Automatic verification of safety and liveness for pipelined machines using WEB refinement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Decision Procedures for the Grand Challenge
Verified Software: Theories, Tools, Experiments
The Challenge of Hardware-Software Co-verification
Verified Software: Theories, Tools, Experiments
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FroCoS '07 Proceedings of the 6th international symposium on Frontiers of Combining Systems
Noetherianity and Combination Problems
FroCoS '07 Proceedings of the 6th international symposium on Frontiers of Combining Systems
Getting Formal Verification into Design Flow
FM '08 Proceedings of the 15th international symposium on Formal Methods
A Practical Approach to Word Level Model Checking of Industrial Netlists
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
EXE: Automatically Generating Inputs of Death
ACM Transactions on Information and System Security (TISSEC)
New results on rewrite-based satisfiability procedures
ACM Transactions on Computational Logic (TOCL)
ATVA '08 Proceedings of the 6th International Symposium on Automated Technology for Verification and Analysis
Reveal: A Formal Verification Tool for Verilog Designs
LPAR '08 Proceedings of the 15th International Conference on Logic for Programming, Artificial Intelligence, and Reasoning
Data Compression for Proof Replay
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Deciding array formulas with frugal axiom instantiation
SMT '08/BPR '08 Proceedings of the Joint Workshops of the 6th International Workshop on Satisfiability Modulo Theories and 1st International Workshop on Bit-Precise Reasoning
Word-level sequential memory abstraction for model checking
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Satisfiability Procedures for Combination of Theories Sharing Integer Offsets
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
A refinement-based compositional reasoning framework for pipelined machine verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated deduction for verification
ACM Computing Surveys (CSUR)
Word level bitwidth reduction for unbounded hardware model checking
Formal Methods in System Design
User control and direction of a more efficient simplifier in ACL2
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Theory decision by decomposition
Journal of Symbolic Computation
A scalable decision procedure for fixed-width bit-vectors
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Making the Most of BMC Counterexamples
Electronic Notes in Theoretical Computer Science (ENTCS)
An Efficient Nelson-Oppen Decision Procedure for Difference Constraints over Rationals
Electronic Notes in Theoretical Computer Science (ENTCS)
Building small equality graphs for deciding equality logic with uninterpreted functions
Information and Computation
Exploiting program dependencies for scalable multiple-path symbolic execution
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Abstraction-based performance verification of NoCs
Proceedings of the 48th Design Automation Conference
Invisible invariants and abstract interpretation
SAS'11 Proceedings of the 18th international conference on Static analysis
Accurate theorem proving for program verification
ISoLA'04 Proceedings of the First international conference on Leveraging Applications of Formal Methods
Zap: automated theorem proving for software analysis
LPAR'05 Proceedings of the 12th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Deciding separation logic formulae by SAT and incremental negative cycle elimination
LPAR'05 Proceedings of the 12th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Pipelined microprocessors optimization and debugging
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Formal verification of a SHA-1 circuit core using ACL2
TPHOLs'05 Proceedings of the 18th international conference on Theorem Proving in Higher Order Logics
FroCoS'05 Proceedings of the 5th international conference on Frontiers of Combining Systems
A logic and decision procedure for predicate abstraction of heap-manipulating programs
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
Yet another decision procedure for equality logic
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
DPLL(T) with exhaustive theory propagation and its application to difference logic
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Decision procedures customized for formal verification
CADE' 20 Proceedings of the 20th international conference on Automated Deduction
Counterexample guided invariant discovery for parameterized cache coherence verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
A parameterized benchmark suite of hard pipelined-machine-verification problems
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Learning conditional abstractions
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Formal verification of infinite state systems using boolean methods
RTA'06 Proceedings of the 17th international conference on Term Rewriting and Applications
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Refinement and theorem proving
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
SDSAT: tight integration of small domain encoding and lazy approaches in a separation logic solver
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Approximating predicate images for bit-vector logic
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Sciduction: combining induction, deduction, and structure for verification and synthesis
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
EPR-based bounded model checking at word level
IJCAR'12 Proceedings of the 6th international joint conference on Automated Reasoning
Cubicle: a parallel SMT-based model checker for parameterized systems: tool paper
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In this paper, we present the logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions (CLU). CLU generalizes the logic of equality with uninterpreted functions (EUF) with constrained lambda expressions, ordering, and successor and predecessor functions. In addition to modeling pipelined processors that EUF has proved useful for, CLU can be used to model many infinite-state systems including those with infinite memories, finite and infinite queues including lossy channels, and networks of identical processes. Even with this richer expressive power, the validity of a CLU formula can be efficiently decided by translating it to a propositional formula, and then using Boolean methods to check validity. We give theoretical and empirical evidence for the efficiency of our decision procedure. We also describe verification techniques that we have used on a variety of systems, including an out-of-order execution unit and the load-store unit of an industrial microprocessor.