Model checking
Formal Equivalence Checking and Design DeBugging
Formal Equivalence Checking and Design DeBugging
ASIAN '97 Proceedings of the Third Asian Computing Science Conference on Advances in Computing Science
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Handbook of automated reasoning
Handbook of automated reasoning
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Automatic memory reductions for RTL model verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Improvements to combinational equivalence checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Decision procedures for extensions of the theory of arrays
Annals of Mathematics and Artificial Intelligence
Decision Procedures: An Algorithmic Point of View
Decision Procedures: An Algorithmic Point of View
Encodings of Bounded LTL Model Checking in Effectively Propositional Logic
CADE-21 Proceedings of the 21st international conference on Automated Deduction: Automated Deduction
iProver --- An Instantiation-Based Theorem Prover for First-Order Logic (System Description)
IJCAR '08 Proceedings of the 4th international joint conference on Automated Reasoning
Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
Finding Loop Invariants for Programs over Arrays Using a Theorem Prover
FASE '09 Proceedings of the 12th International Conference on Fundamental Approaches to Software Engineering: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009
Deciding Effectively Propositional Logic Using DPLL and Substitution Sets
Journal of Automated Reasoning
The 5th IJCAR automated theorem proving system competition - CASC-J5
AI Communications
SAT-based model checking without unrolling
VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
Encoding industrial hardware verification problems into effectively propositional logic
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
ASASP: automated symbolic analysis of security policies
CADE'11 Proceedings of the 23rd international conference on Automated deduction
What's decidable about arrays?
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
Implicative simultaneous satisfiability and applications
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
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We propose a word level, bounded model checking (BMC) algorithm based on translation into the effectively propositional fragment (EPR) of first-order logic. This approach to BMC allows for succinct representation of unrolled transition systems and facilitates reasoning at a higher level of abstraction. We show that the proposed approach can be scaled to industrial hardware model checking problems involving memories and bit-vectors. Another contribution of this work is in generating challenging benchmarks for first-order theorem provers based on the proposed encoding of real-life hardware verification problems into EPR. We report experimental results for these problems for several provers known to be strong in EPR problem solving. A number of these benchmarks have already been released to the TPTP library.